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1.发明申请METHOD AND CIRCUIT FOR LOCAL CLOCK GENERATION AND SMARTCARD INCLUDING IT THEREON 审中-公开用于本地时钟产生的方法和电路以及包括它的智能卡
公开(公告)号：WO2007042928A2
公开(公告)日：2007-04-19
申请号：PCT/IB2006002860
申请日：2006-10-06
Applicant: AXALTO SA , ST MICROELECTRONICS SA , LEYDIER ROBERT , POMET ALAIN , DUVAL BENJAMIN
Inventor： LEYDIER ROBERT , POMET ALAIN , DUVAL BENJAMIN
CPC classification number: G06F1/04 , H03K5/133 , H03K5/135 , H03K5/156 , H03K2005/00058 , H04L7/0338
Abstract: One delay circuit is inserted in open loop inside a clock recovery circuit for improving the accuracy of clock recovery. One oscillator signal f(0) to f(2 i -1) is provided with a basic Step of Time. A rational number of Step of Time corresponding to a bit-duration is measured inside a received flow of bits. The oscillator signal f(0) to j(2 i -1) is transformed into a clock signal CK having active edges of said clock signal in phase with at least one oscillator signal f(0) to f(2 i -1), two consecutive active edges being separated by a time duration proportional to the integer part of the number of Step of Time. A time delay is computed proportional to the fractional part of the number of Step of Time. The next active edge of the clock signal CK is delayed of said computed delay.
Abstract translation: 一个延迟电路插入时钟恢复电路内的开环，以提高时钟恢复的精度。 一个振荡器信号f（0）至f（2-i-1）被提供有基本的时间步长。 在接收到的比特流内测量与比特持续时间相对应的时间步长的合理数量。 振荡器信号f（0）至j（2≤I-1）被变换成具有与所述时钟信号的有效边沿同时具有至少一个振荡器信号f（0）至f （2 i），两个连续的有效边缘被分离成与时间步长数的整数部分成比例的时间长度。 计算时间延迟与时间步长数的小数部分成比例。 时钟信号CK的下一个有效沿延迟所述计算的延迟。
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公开(公告)号：DE60107106T2
公开(公告)日：2005-11-03
申请号：DE60107106
申请日：2001-08-30
Inventor： FRUHAUF F , GOUPIL HERVE , LEYDIER ROBERT
Abstract: A dual-mode IC is provided for operating in first mode such as an ISO mode in accordance with International Standards Organization 7816 (ISO 7816) protocol, and a second, non-ISO mode, such as a USB mode in accordance with Universal Serial Bus (USB) protocol. The dual-mode IC is preferably in a smart card and includes a microprocessor, a switching block, and an external interface. The external interface includes a voltage supply pad, a reference voltage pad, a reset pad, a clock pad and an input/output pad in accordance with the ISO 7816 protocol, and a D-plus pad and D-minus pad in accordance with the USB protocol. The IC further includes a mode configuration circuit for detecting a USB mode condition on at least one of the D-plus and D-minus pads, and configuring the IC in the ISO mode or the USB mode depending on the result. Once the IC is configured in a particular mode, it will operate in only that mode until the next power-on reset sequence.
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公开(公告)号：SG146444A1
公开(公告)日：2008-10-30
申请号：SG2006030605
申请日：2002-11-06
Applicant: AXALTO SA
Inventor： BONVALOT BEATRICE , BARBE SYLVIE , LEMOULLEC LAURENT , LEYDIER ROBERT
Abstract: A Method Of Manufacturing A Plurality Of Assemblies A plurality of assemblies is manufactured. Each assembly comprises a sealing slice that is fixed to a base slice. The plurality of assemblies is manufactured in the following manner. In a preparation step, a stack is formed. The stack comprises a plurality of pre-assemblies. Each pre-assembly comprises a base slice, a sealing slice and a fixing layer provided between the base slice and the sealing slice. The stack further comprises at least one supple buffer layer. The supple buffer layer has a mechanical rigidity, which is substantially less than that of the base slices and that of the sealing slices. The supple buffer layer thus enables to compensate for variations in thickness of the base slices and of the sealing slices. In a fixing step, the stack is pressed which causes the sealing slice of each pre- assembly to be fixed to the base-slice of the pre-assembly.
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公开(公告)号：DE602005005002T2
公开(公告)日：2008-08-28
申请号：DE602005005002
申请日：2005-01-05
Applicant: AXALTO SA , ST MICROELECTRONICS SA
Inventor： LEYDIER ROBERT , POMET ALAIN
Abstract: A data communication device comprises an input circuit (DRTC) that converts external data (XDT) into internal data (IDT) on the basis of a sampling signal (SP). A synchronization circuit (SYNC) provides the sampling signal (SP) on the basis of an oscillator signal (OS) and a synchronization value (SV). The synchronization value (SV) is representative of a number of cycles of the oscillator signal (OS) contained within a time interval for a unit of external data. The synchronization value (SV) is an initial value (IV) during an initial synchronization phase and a measured value (MV) during a measurement-based synchronization phase. A control circuit (IFC) carries out a calibration step in which the initial value (IV) is a preprogrammed reset value (RV) and in which the measured value (MV) is stored as a calibration value (CV). The control circuit (IFC) applies the calibration value (CV) as the initial value (IV) in subsequent initial synchronization phases.
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公开(公告)号：DE69838507D1
公开(公告)日：2007-11-15
申请号：DE69838507
申请日：1998-08-06
Applicant: AXALTO SA
Inventor： BONVALOT BEATRICE , LEYDIER ROBERT
IPC: B42D15/10 , H01L23/58 , G06K19/073 , G06K19/077 , H01L21/314 , H01L23/29 , H01L23/31
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Patent Agency Ranking
公开(公告)号：DE69923380D1
公开(公告)日：2005-03-03
申请号：DE69923380
申请日：1999-06-15
Applicant: AXALTO SA
Inventor： LEYDIER ROBERT
Abstract: The system uses pairs of lines to avoid risk of erroneous data recording. The integrated circuit which is incorporated into a smart card comprising a central processing unit (CPU), memories (RAM, ROM and EEPROM) and a data input/output pad (I/O). n address bus lines (A0... A15) and p data bus lines (D0..
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公开(公告)号：DE60107106D1
公开(公告)日：2004-12-16
申请号：DE60107106
申请日：2001-08-30
Inventor： FRUHAUF F , GOUPIL HERVE , LEYDIER ROBERT
Abstract: A dual-mode IC is provided for operating in first mode such as an ISO mode in accordance with International Standards Organization 7816 (ISO 7816) protocol, and a second, non-ISO mode, such as a USB mode in accordance with Universal Serial Bus (USB) protocol. The dual-mode IC is preferably in a smart card and includes a microprocessor, a switching block, and an external interface. The external interface includes a voltage supply pad, a reference voltage pad, a reset pad, a clock pad and an input/output pad in accordance with the ISO 7816 protocol, and a D-plus pad and D-minus pad in accordance with the USB protocol. The IC further includes a mode configuration circuit for detecting a USB mode condition on at least one of the D-plus and D-minus pads, and configuring the IC in the ISO mode or the USB mode depending on the result. Once the IC is configured in a particular mode, it will operate in only that mode until the next power-on reset sequence.
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公开(公告)号：FR2896057A1
公开(公告)日：2007-07-13
申请号：FR0600251
申请日：2006-01-12
Applicant: ST MICROELECTRONICS SA , AXALTO SA
Inventor： POMET ALAIN , DUVAL BENJAMIN , LEYDIER ROBERT
Abstract: L'invention concerne un procédé de génération d'un nombre aléatoire, comprenant des étapes de réception d'un signal binaire (RxD) de transmission de données soumis à une fluctuation de phase, de génération de plusieurs signaux d'oscillateur (P0-P7) sensiblement de même fréquence moyenne et ayant des phases respectives distinctes, de prélèvement d'un état (S0-S7) de chacun des signaux d'oscillateur à l'apparition de fronts du signal binaire (RxD), et d'élaboration d'un nombre aléatoire (RND) à partir des états de chacun des signaux d'oscillateur. Application à un circuit intégré utilisable dans une carte à puce.
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公开(公告)号：DE602005005002D1
公开(公告)日：2008-04-10
申请号：DE602005005002
申请日：2005-01-05
Applicant: AXALTO SA , ST MICROELECTRONICS SA
Inventor： LEYDIER ROBERT , POMET ALAIN
Abstract: A data communication device comprises an input circuit (DRTC) that converts external data (XDT) into internal data (IDT) on the basis of a sampling signal (SP). A synchronization circuit (SYNC) provides the sampling signal (SP) on the basis of an oscillator signal (OS) and a synchronization value (SV). The synchronization value (SV) is representative of a number of cycles of the oscillator signal (OS) contained within a time interval for a unit of external data. The synchronization value (SV) is an initial value (IV) during an initial synchronization phase and a measured value (MV) during a measurement-based synchronization phase. A control circuit (IFC) carries out a calibration step in which the initial value (IV) is a preprogrammed reset value (RV) and in which the measured value (MV) is stored as a calibration value (CV). The control circuit (IFC) applies the calibration value (CV) as the initial value (IV) in subsequent initial synchronization phases.
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公开(公告)号：AT387771T
公开(公告)日：2008-03-15
申请号：AT05290013
申请日：2005-01-05
Applicant: AXALTO SA , ST MICROELECTRONICS SA
Inventor： LEYDIER ROBERT , POMET ALAIN
Abstract: A data communication device comprises an input circuit (DRTC) that converts external data (XDT) into internal data (IDT) on the basis of a sampling signal (SP). A synchronization circuit (SYNC) provides the sampling signal (SP) on the basis of an oscillator signal (OS) and a synchronization value (SV). The synchronization value (SV) is representative of a number of cycles of the oscillator signal (OS) contained within a time interval for a unit of external data. The synchronization value (SV) is an initial value (IV) during an initial synchronization phase and a measured value (MV) during a measurement-based synchronization phase. A control circuit (IFC) carries out a calibration step in which the initial value (IV) is a preprogrammed reset value (RV) and in which the measured value (MV) is stored as a calibration value (CV). The control circuit (IFC) applies the calibration value (CV) as the initial value (IV) in subsequent initial synchronization phases.
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