公开(公告)号：DE69129361T2

公开(公告)日：1998-11-05

申请号：DE69129361

申请日：1991-12-23

Applicant: ADVANTEST CORP

Inventor： NUKUI YOSHIHIRO

IPC: H03H21/00 ,  H03H17/00 ,  H03H17/06

Abstract: Digital data provided in the form of a serial signal (S(i)) is fetched into an N-bit shift register (11) and parallel N-bit data output therefrom is provided as address data to address input terminals of a memory (21). In the memory there are prestored at respective addresses defined by the N-bit data the total sum value of multiplied outputs obtained by multiplying the address values and the bit data of a coefficient h(n-i) defining an impulse response characteristic. The N-bit data is provided to an address input terminal (A0-An-1) of the memory to read out therefrom a digital value corresponding to the output voltage of a digital filter. The digital value is D/A converted to obtain the output voltage of the digital filter.

公开(公告)号：DE69129361D1

公开(公告)日：1998-06-10

申请号：DE69129361

申请日：1991-12-23

Applicant: ADVANTEST CORP

Inventor： NUKUI YOSHIHIRO

IPC: H03H21/00 ,  H03H17/00 ,  H03H17/06

Abstract: Digital data provided in the form of a serial signal (S(i)) is fetched into an N-bit shift register (11) and parallel N-bit data output therefrom is provided as address data to address input terminals of a memory (21). In the memory there are prestored at respective addresses defined by the N-bit data the total sum value of multiplied outputs obtained by multiplying the address values and the bit data of a coefficient h(n-i) defining an impulse response characteristic. The N-bit data is provided to an address input terminal (A0-An-1) of the memory to read out therefrom a digital value corresponding to the output voltage of a digital filter. The digital value is D/A converted to obtain the output voltage of the digital filter.

公开(公告)号：DE69200189T2

公开(公告)日：1994-11-17

申请号：DE69200189

申请日：1992-02-17

Applicant: ADVANTEST CORP

Inventor： NUKUI YOSHIHIRO

IPC: H03L7/093 ,  H03D13/00 ,  H03L7/089

公开(公告)号：DE69200189D1

公开(公告)日：1994-07-21

申请号：DE69200189

申请日：1992-02-17

Applicant: ADVANTEST CORP

Inventor： NUKUI YOSHIHIRO

IPC: H03L7/093 ,  H03D13/00 ,  H03L7/089

公开(公告)号：AU9008191A

公开(公告)日：1992-07-09

申请号：AU9008191

申请日：1991-12-23

Applicant: ADVANTEST CORP

Inventor： NUKUI YOSHIHIRO

IPC: H03H21/00 ,  H03H17/00 ,  H03H17/06 ,  H03H17/02

Abstract: Digital data provided in the form of a serial signal (S(i)) is fetched into an N-bit shift register (11) and parallel N-bit data output therefrom is provided as address data to address input terminals of a memory (21). In the memory there are prestored at respective addresses defined by the N-bit data the total sum value of multiplied outputs obtained by multiplying the address values and the bit data of a coefficient h(n-i) defining an impulse response characteristic. The N-bit data is provided to an address input terminal (A0-An-1) of the memory to read out therefrom a digital value corresponding to the output voltage of a digital filter. The digital value is D/A converted to obtain the output voltage of the digital filter.

公开(公告)号：CA2058310A1

公开(公告)日：1992-06-29

申请号：CA2058310

申请日：1991-12-23

Applicant: ADVANTEST CORP

Inventor： NUKUI YOSHIHIRO

IPC: H03H21/00 ,  H03H17/00 ,  H03H17/06 ,  H03H17/02

Abstract: Digital data provided in the form of a serial signal is fetched into an N-bit shift register and parallel N-bit data output therefrom is provided as address data to address input terminals of a memory. In the memory there are prestored at respective addresses defined by the N-bit data the total sum value of multiplied outputs obtained by multiplying the address values and the bit data of a coefficient h(n-i) defining an impulse response characteristic. The N-bit data is provided to an address input terminal of the memory to read out therefrom a digital value corresponding to the output voltage of a digital filter. The digital value is D/A converted to obtain the output voltage of the digital filter.

公开(公告)号：JPS6189563A

公开(公告)日：1986-05-07

申请号：JP21209084

申请日：1984-10-08

Applicant: Advantest Corp

Inventor： KURIHARA TAKENORI ,  NUKUI YOSHIHIRO ,  KUME DANJI

IPC: G01R23/173 ,  G01R27/28

Abstract: PURPOSE: To make it possible to read both of the entire magnitude of a frequency spectrum having a large peak value and the magnitude of a frequency spectrum having a small level by one picture, by changing over the gain of an IF amplifier in the upper and lower sides of the frequence spectrum.
CONSTITUTION: When a detection output component reached a predetermined level, the gain of an IF amplifier is changed over. For example, when a frequency spectrum is displayed, the gain of the IF amplifier is changed over in the upper and lower sides of the frequency spectrum and, at the time of a side desired to be observed in an enlarged state, the gain of the IF amplifier is set to 'large'. In a side wanting to observe the whole of a frequency spectrum having a large peak value, the gain of the IF amplifier is throttled small. Therefore, a necessary part is enlarged on the display surface of CRT and the whole of the frequency spectrum can be also displayed.
COPYRIGHT: (C)1986,JPO&Japio

Abstract translation: 目的：通过改变上部的IF放大器的增益，可以读取具有较大峰值的频谱的整个幅度和具有小电平的频谱的幅度两幅图像， 频谱的下侧。 构成：当检测输出分量达到预定电平时，IF放大器的增益被切换。 例如，当显示频谱时，IF放大器的增益在频谱的上侧和下侧被切换，并且在希望在放大状态下观察的一侧的时候，增益 IF放大器设置为“大”。 在想要观察整个具有大峰值的频谱的方面，IF放大器的增益被减小。 因此，在CRT的显示面上放大必要部分，也可以显示整个频谱。

公开(公告)号：JPH04270510A

公开(公告)日：1992-09-25

申请号：JP40909490

申请日：1990-12-28

Applicant: ADVANTEST CORP

Inventor： NUKUI YOSHIHIRO

IPC: H03H21/00 ,  H03H17/00 ,  H03H17/06

Abstract: PURPOSE:To realize the digital filter able to attain high speed response. CONSTITUTION:A digital data given in terms of a serial signal is fetched by an N-bit shift register 1. A parallel bit data outputted from the N-bit shift register 1 is given to an address input terminal of a memory 10. A coefficient h(n) specifying an impulse response characteristic is multiplied with each bit data of an address signal in each address of the memory 10 depending on the N-bit data and the total sum of the result of multiplication is stored. The N-bit data is given to an address input terminal of the memory 10 to read a digital value corresponding to an output voltage of the digital filter from the memory 10. The digital value is D/A-converted to obtain an output voltage of the digital filter.

公开(公告)号：JPS59214774A

公开(公告)日：1984-12-04

申请号：JP8543083

申请日：1983-05-16

Applicant: Advantest Corp

Inventor： NUKUI YOSHIHIRO

IPC: G01R19/04

Abstract: PURPOSE: To eliminate the outputting of a false peak voltage by providing a slope detection circuit for discriminating the leading edge and the tailing edge of a signal to be observed to reset a positive/negative peak holding circuit at a positive or negative peak point.
CONSTITUTION: A slope detector 400 and a reset pulse generation means 401 are provided. Even when a positive peak holding circuit 103 is reset to a false voltage E
6 at the time T
4 , the hold voltage is reset to a negative peak at the time T
4 ' and the circuit 103 holds a normal peak voltage E
9 at the time T
6 , hence not a false peak voltage. The negative peak holding circuit 104 does the same. Thus, no false voltage will be outputted for the sample holding 106.
COPYRIGHT: (C)1984,JPO&Japio

Abstract translation: 目的：通过提供用于鉴别要观察的信号的前沿和后端的斜率检测电路来消除误峰值电压的输出，以在正或负峰值点复位正/负峰值保持电路。 构成：提供斜率检测器400和复位脉冲产生装置401。 即使在时刻T4将正峰值保持电路103复位为假电压E6时，在时刻T4'将保持电压复位为负峰值，电路103在时刻T6保持正常峰值电压E9，因此 不是假峰值电压。 负峰值保持电路104进行相同的操作。 因此，样品保持体106不会输出假电压。

公开(公告)号：JPH04262618A

公开(公告)日：1992-09-18

申请号：JP2344991

申请日：1991-02-18

Applicant: ADVANTEST CORP

Inventor： NUKUI YOSHIHIRO

IPC: H03L7/093 ,  H03D13/00 ,  H03L7/089

Abstract: PURPOSE:To prevent the gain from being decreased even when the phase difference of two inputted signals is nearly O by adding a prescribed pulse width to a pulse having a pulse width corresponding to the phase difference of the two signals. CONSTITUTION:A delay detection circuit 15 to detect the arrival of a delay signal between two signals fv, fr and a pulse addition circuit 16 adding a pulse having a prescribed pulse width to a phase difference signal outputted from a phase difference detector 10 when the delay detection circuit 15 detects a delay signal are provided between the phase detector 10 and an analog computing element 14. A delay signal ffv or ffr having a prescribed pulse width is added to phase difference signals Av, Ar and the resulting signals are inputted to the analog computing element 14. Thus, even when the phase difference between the input signals fv and fr is close to zero, the analog computing element 14 receives the delay signal ffv or ffr with a prescribed pulse width without fail.