Common-gate comparator and fuse reader

    公开(公告)号:US10854306B1

    公开(公告)日:2020-12-01

    申请号:US16576216

    申请日:2019-09-19

    Abstract: A state of one or more fuses can be determined using a common-gate FET device to read reference information and test information from a fuse bank. In an example, the FET device can be selectively diode-connected using a first switch that responds to a control signal, and a signal-storing capacitor can be connected to the gate terminal of the FET device. The capacitor can store information about a reference signal when the first switch is closed and a first input signal is applied at a source node of the FET device. When the first switch is open, a second input signal can be applied at the source node of the FET device, and an output signal at the drain node of the FET device can indicate a magnitude relationship between the first input signal and the reference signal. In an example, the second input signal can indicate a state of a fuse.

    Utilizing current memory property in current steering digital-to-analog converters

    公开(公告)号:US10819365B1

    公开(公告)日:2020-10-27

    申请号:US16783442

    申请日:2020-02-06

    Abstract: Improved switching techniques for controlling three-level current steering DAC cells are disclosed. The techniques include decoupling two current sources, implemented as field-effect transistors (FETs), of a DAC cell both from their respective bias sources and from a load for converting a zero digital input, where the decoupling is performed in a certain order. The techniques also include coupling the current sources to their respective bias sources and to the load for converting a non-zero digital input, where the coupling is also performed in a certain order. The certain order of decoupling and coupling the bias sources and the load to the current sources of a DAC cell are based on the phenomenon of current memory in FETs. Utilizing current memory when operating a DAC cell may allow reducing power consumption while preserving the high performance properties of a three-level current steering DAC.

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