中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

11 records (took 0.028 seconds)

    Tilt Mode Accelerometer with improved Offset and Noise Performance
    1.
    发明申请
    Tilt Mode Accelerometer with improved Offset and Noise Performance 有权
    倾斜模式加速度计具有改进的偏移和噪声性能

    公开(公告)号：US20140251011A1

    公开(公告)日：2014-09-11

    申请号：US13785624

    申请日：2013-03-05

    Applicant: ANALOG DEVICES, INC.

    Inventor： Xin Zhang ,  Howard R. Samuels ,  Michael W. Judy

    IPC: G01P15/125 ,  G01P15/08

    CPC classification number: G01P15/125 ,  G01P15/08 ,  G01P2015/0831 ,  G01P2015/0834

    Abstract: A single-axis tilt-mode microelectromechanical accelerometer structure. The structure includes a substrate having a top surface defined by a first end and a second end. Coupled to the substrate is a first asymmetrically-shaped mass suspended above the substrate pivotable about a first pivot point on the substrate between the first end and the second end and a second asymmetrically-shaped mass suspended above the substrate pivotable about a second pivot point on the substrate between the first end and the second end. The structure also includes a first set of electrodes positioned on the substrate and below the first asymmetrically-shaped mass and a second set of electrodes positioned on the substrate and below the second asymmetrically-shaped mass.

    Abstract translation: 单轴倾斜模式微机电加速度计结构。 该结构包括具有由第一端和第二端限定的顶表面的基底。 耦合到衬底的是第一不对称形状的质量块，悬挂在衬底上方，可在第一端和第二端之间围绕衬底上的第一枢转点枢转，并且悬挂在衬底上方的第二不对称形状的质量可围绕第二枢转点枢转 第一端和第二端之间的衬底。 该结构还包括位于衬底上并位于第一不对称形状的质量下方的第一组电极和位于衬底上并位于第二不对称形状的质量下方的第二组电极。

    Built-In Self Test for One-Time-Programmable Memory
    2.
    发明申请
    Built-In Self Test for One-Time-Programmable Memory 有权
    一次性可编程存储器的内置自检

    公开(公告)号：US20130294143A1

    公开(公告)日：2013-11-07

    申请号：US13936313

    申请日：2013-07-08

    Applicant: Analog Devices, Inc.

    Inventor： James M. Lee ,  Howard R. Samuels ,  Thomas W. Kelly

    IPC: G11C29/02 ,  G11C17/18

    CPC classification number: G11C29/021 ,  G11C17/14 ,  G11C17/18 ,  G11C29/02 ,  G11C29/027 ,  G11C29/50 ,  G11C29/50008 ,  G11C2029/5006

    Abstract: An apparatus and method of testing one-time-programmable memory provides one-time-programmable memory having one or more memory locations for storing data and corresponding programming circuitry for each memory location. In addition, each programming circuitry has a circuit element configured to permanently change state to store the data in the memory. The method also reads each memory location to verify that the memory location is unprogrammed and activates the programming circuitry for each memory location, which applies a test current to the programming circuitry. The test current is less than a threshold current needed to permanently change the state of the circuit element. The method then determines whether the programming circuitry is functioning properly.

    Abstract translation: 测试一次可编程存储器的装置和方法提供具有用于存储数据的一个或多个存储器位置的一次可编程存储器和用于每个存储器位置的对应编程电路。 此外，每个编程电路具有被配置为永久地改变状态以将数据存储在存储器中的电路元件。 该方法还读取每个存储器位置以验证存储器位置是否未编程，并激活每个存储器位置的编程电路，其将测试电流施加到编程电路。 测试电流小于永久改变电路元件状态所需的阈值电流。 然后该方法确定编程电路是否正常工作。

    Electronic switch exhibiting low off-state leakage current
    3.
    发明授权
    Electronic switch exhibiting low off-state leakage current 有权

    公开(公告)号：US10210946B2

    公开(公告)日：2019-02-19

    申请号：US15338278

    申请日：2016-10-28

    Applicant: Analog Devices, Inc.

    Inventor： Howard R. Samuels

    IPC: H03K17/687 ,  G11C27/02 ,  H03K17/10 ,  H03K17/693

    Abstract: According to some aspects, a low-leakage switch is provided. In some embodiments, the low-leakage switch includes a plurality of pass transistors in series that selectively couple two ports of the low-leakage switch and a node biasing circuit coupled to a node between the plurality of pass transistors. In these embodiments, the node biasing circuit may adjust a voltage at the node to change the gate-to-source voltage of the pass transistors and, thereby, reduce the leakage current through the pass transistors when the low-leakage switch is turned off. The node biasing circuit may also include circuitry to reduce the leakage current introduced by the node biasing circuit into the node when the low-leakage switch is turned on.

    Built-in self test for one-time-programmable memory
    5.
    发明授权
    Built-in self test for one-time-programmable memory 有权
    内置自检一次性可编程存储器

    公开(公告)号：US08665627B2

    公开(公告)日：2014-03-04

    申请号：US13936313

    申请日：2013-07-08

    Applicant: Analog Devices, Inc.

    Inventor： James M. Lee ,  Howard R. Samuels ,  Thomas W. Kelly

    IPC: G11C17/00

    CPC classification number: G11C29/021 ,  G11C17/14 ,  G11C17/18 ,  G11C29/02 ,  G11C29/027 ,  G11C29/50 ,  G11C29/50008 ,  G11C2029/5006

    Abstract: An apparatus and method of testing one-time-programmable memory provides one-time-programmable memory having one or more memory locations for storing data and corresponding programming circuitry for each memory location. In addition, each programming circuitry has a circuit element configured to permanently change state to store the data in the memory. The method also reads each memory location to verify that the memory location is unprogrammed and activates the programming circuitry for each memory location, which applies a test current to the programming circuitry. The test current is less than a threshold current needed to permanently change the state of the circuit element. The method then determines whether the programming circuitry is functioning properly.

    Abstract translation: 测试一次可编程存储器的装置和方法提供具有用于存储数据的一个或多个存储器位置的一次可编程存储器和用于每个存储器位置的对应编程电路。 此外，每个编程电路具有被配置为永久地改变状态以将数据存储在存储器中的电路元件。 该方法还读取每个存储器位置以验证存储器位置是否未编程，并激活每个存储器位置的编程电路，其将测试电流施加到编程电路。 测试电流小于永久改变电路元件状态所需的阈值电流。 然后该方法确定编程电路是否正常工作。

    Common-gate comparator and fuse reader
    7.
    发明授权
    Common-gate comparator and fuse reader 有权

    公开(公告)号：US10854306B1

    公开(公告)日：2020-12-01

    申请号：US16576216

    申请日：2019-09-19

    Applicant: Analog Devices, Inc.

    Inventor： Howard R. Samuels ,  Long Pham

    IPC: G11C17/18 ,  G11C7/06 ,  G11C7/10 ,  G11C17/16 ,  G11C7/08 ,  G11C29/02

    Abstract: A state of one or more fuses can be determined using a common-gate FET device to read reference information and test information from a fuse bank. In an example, the FET device can be selectively diode-connected using a first switch that responds to a control signal, and a signal-storing capacitor can be connected to the gate terminal of the FET device. The capacitor can store information about a reference signal when the first switch is closed and a first input signal is applied at a source node of the FET device. When the first switch is open, a second input signal can be applied at the source node of the FET device, and an output signal at the drain node of the FET device can indicate a magnitude relationship between the first input signal and the reference signal. In an example, the second input signal can indicate a state of a fuse.

    ELECTRONIC SWITCH EXHIBITING LOW OFF-STATE LEAKAGE CURRENT
    8.
    发明申请
    ELECTRONIC SWITCH EXHIBITING LOW OFF-STATE LEAKAGE CURRENT 审中-公开

    公开(公告)号：US20180013417A1

    公开(公告)日：2018-01-11

    申请号：US15338278

    申请日：2016-10-28

    Applicant: Analog Devices, Inc.

    Inventor： Howard R. Samuels

    IPC: H03K17/12 ,  H03K17/687 ,  G11C27/02

    CPC classification number: G11C27/02 ,  H03K17/102 ,  H03K17/693 ,  H03K2217/0036 ,  H03K2217/0054

    Abstract: According to some aspects, a low-leakage switch is provided. In some embodiments, the low-leakage switch includes a plurality of pass transistors in series that selectively couple two ports of the low-leakage switch and a node biasing circuit coupled to a node between the plurality of pass transistors. In these embodiments, the node biasing circuit may adjust a voltage at the node to change the gate-to-source voltage of the pass transistors and, thereby, reduce the leakage current through the pass transistors when the low-leakage switch is turned off. The node biasing circuit may also include circuitry to reduce the leakage current introduced by the node biasing circuit into the node when the low-leakage switch is turned on.

    Tilt mode accelerometer with improved offset and noise performance
    9.
    发明授权
    Tilt mode accelerometer with improved offset and noise performance 有权
    倾斜模式加速度计具有改善的偏移和噪声性能

    公开(公告)号：US09297825B2

    公开(公告)日：2016-03-29

    申请号：US13785624

    申请日：2013-03-05

    Applicant: Analog Devices, Inc.

    Inventor： Xin Zhang ,  Howard R. Samuels ,  Michael W. Judy

    IPC: G01P15/125 ,  G01P15/08

    CPC classification number: G01P15/125 ,  G01P15/08 ,  G01P2015/0831 ,  G01P2015/0834

    Abstract: A single-axis tilt-mode microelectromechanical accelerometer structure. The structure includes a substrate having a top surface defined by a first end and a second end. Coupled to the substrate is a first asymmetrically-shaped mass suspended above the substrate pivotable about a first pivot point on the substrate between the first end and the second end and a second asymmetrically-shaped mass suspended above the substrate pivotable about a second pivot point on the substrate between the first end and the second end. The structure also includes a first set of electrodes positioned on the substrate and below the first asymmetrically-shaped mass and a second set of electrodes positioned on the substrate and below the second asymmetrically-shaped mass.

    Abstract translation: 单轴倾斜模式微机电加速度计结构。 该结构包括具有由第一端和第二端限定的顶表面的基底。 耦合到衬底的是第一不对称形状的质量块，悬挂在衬底上方，可在第一端和第二端之间围绕衬底上的第一枢转点枢转，并且悬挂在衬底上方的第二不对称形状的质量可围绕第二枢转点枢转 第一端和第二端之间的衬底。 该结构还包括位于衬底上并位于第一不对称形状的质量下方的第一组电极和位于衬底上并位于第二不对称形状的质量下方的第二组电极。

    Low Noise Amplifier for Multiple Channels
    10.
    发明申请
    Low Noise Amplifier for Multiple Channels 有权
    多通道低噪声放大器

    公开(公告)号：US20150256133A1

    公开(公告)日：2015-09-10

    申请号：US14718328

    申请日：2015-05-21

    Applicant: Analog Devices, Inc.

    Inventor： Howard R. Samuels

    IPC: H03F1/26 ,  H03F3/04

    CPC classification number: H03F1/26 ,  G01P15/125 ,  G01P15/18 ,  G01P2015/082 ,  H03F3/04 ,  H03F3/45071 ,  H03F3/45475 ,  H03F3/68 ,  H03F2200/129 ,  H03F2200/171 ,  H03F2200/261 ,  H03F2200/333 ,  H03F2203/45512 ,  H03F2203/45544

    Abstract: An amplifier system has an amplifier for amplifying a plurality of input signals from a plurality of different channels, and a plurality of demodulators each operatively coupled with the amplifier for receiving amplified input signals from the amplifier. Each demodulator is configured to demodulate a single amplified input channel signal from a single channel of the plurality of different channels. The system thus also has a plurality of filters, coupled with each of the demodulators, for mitigating the noise.

    Abstract translation: 放大器系统具有用于放大来自多个不同通道的多个输入信号的放大器，以及多个解调器，每个解调器与放大器可操作地耦合，用于从放大器接收放大的输入信号。 每个解调器被配置为从多个不同信道中的单个信道解调单个放大的输入信道信号。 因此，该系统还具有与每个解调器耦合的多个滤波器，以减轻噪声。

Patent Agency Ranking