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    POWER SAVING OPTIMIZATION FOR HIGH-MOBILITY SCENARIOS
    1.
    发明公开
    POWER SAVING OPTIMIZATION FOR HIGH-MOBILITY SCENARIOS 审中-公开

    公开(公告)号：US20240107613A1

    公开(公告)日：2024-03-28

    申请号：US18371771

    申请日：2023-09-22

    Applicant: Apple Inc.

    Inventor： Bingyin Cui ,  Cheng Li ,  Han Pu ,  Lele Cui ,  Muthukumaran Dhanapal

    IPC: H04W76/20 ,  H04W28/082

    CPC classification number: H04W76/20 ,  H04W28/082

    Abstract: Disclosed are methods, systems, and computer-readable medium to perform operations including: determining that a user equipment (UE) is connected to a cell of a network using a connection in a standalone (SA) mode; based on determining a bandwidth part (BWP) of the connection, accessing a physical cell identifier (PCI) list associated with the UE for a time period; based on the number of PCI values in the list and a duration of the time period, assigning, to a BWP switch timer, a timeout value; initiating the BWP switch timer; and in response to determining that the handover of the UE to the different cell of the network occurs prior to the BWP switch timer reaching the timeout value, causing the UE to switch to a LTE mode.

    Cache arbitration for address translation requests
    2.
    发明授权
    Cache arbitration for address translation requests 有权

    公开(公告)号：US11467959B1

    公开(公告)日：2022-10-11

    申请号：US17324824

    申请日：2021-05-19

    Applicant: Apple Inc.

    Inventor： Winnie W. Yeung ,  Cheng Li

    IPC: G06F12/0802 ,  G06F12/1027

    Abstract: Techniques are disclosed relating to caching for address translation. In some embodiments, address translation circuitry is configured to process requests to translate addresses in a first address space to addresses in a second address space. The translation circuitry may include cache circuitry configured to store translation information, arbitration circuitry configured to arbitrate among ready requests for access to entries of the cache, and hazard circuitry. The hazard circuitry may assign a first request to an ready status the arbitration circuitry based on detection of an absence of hazards for a first address of the first request and add a second request to a queue of requests for the arbitration circuitry based on detection of a hazard for a second address of the second request. Independent arbitration for requests without hazards may improve performance in various aspects, relative to traditional techniques.

    Multi-block cache fetch techniques
    4.
    发明授权
    Multi-block cache fetch techniques 有权

    公开(公告)号：US12248399B2

    公开(公告)日：2025-03-11

    申请号：US17324800

    申请日：2021-05-19

    Applicant: Apple Inc.

    Inventor： Winnie W. Yeung ,  Cheng Li

    IPC: G06F12/0811 ,  G06F12/02 ,  G06F12/0846 ,  G06F12/0891 ,  G06F13/16

    Abstract: Techniques are disclosed relating to multi-block fetches for cache misses. In some embodiments, cache tag circuitry maintains a tag value that is shared by multiple cache blocks. In response to a miss, the cache may initiate a fetch request to a next level cache or memory. Aggregation circuitry may aggregate multiple fetch requests for cache blocks that share the tag value and fetch circuitry may initiate a single multi-block fetch operation to the next level cache or memory that returns cache blocks for the aggregated multiple fetch requests. In various embodiments, disclosed techniques may improve performance (e.g., by reducing fetch bus transactions), reduce power consumption, or both, relative to traditional techniques.

    Multi-block Cache Fetch Techniques
    5.
    发明申请
    Multi-block Cache Fetch Techniques 有权

    公开(公告)号：US20220374359A1

    公开(公告)日：2022-11-24

    申请号：US17324800

    申请日：2021-05-19

    Applicant: Apple Inc.

    Inventor： Winnie W. Yeung ,  Cheng Li

    IPC: G06F12/0811 ,  G06F12/0846 ,  G06F12/0891 ,  G06F12/02 ,  G06F13/16

    Abstract: Techniques are disclosed relating to multi-block fetches for cache misses. In some embodiments, cache tag circuitry maintains a tag value that is shared by multiple cache blocks. In response to a miss, the cache may initiate a fetch request to a next level cache or memory. Aggregation circuitry may aggregate multiple fetch requests for cache blocks that share the tag value and fetch circuitry may initiate a single multi-block fetch operation to the next level cache or memory that returns cache blocks for the aggregated multiple fetch requests. In various embodiments, disclosed techniques may improve performance (e.g., by reducing fetch bus transactions), reduce power consumption, or both, relative to traditional techniques.

    Cache footprint management
    7.
    发明授权
    Cache footprint management 有权

    公开(公告)号：US11947462B1

    公开(公告)日：2024-04-02

    申请号：US17653418

    申请日：2022-03-03

    Applicant: Apple Inc.

    Inventor： Yoong Chert Foo ,  Terence M. Potter ,  Donald R. DeSota ,  Benjiman L. Goodman ,  Aroun Demeure ,  Cheng Li ,  Winnie W. Yeung

    IPC: G06F12/08 ,  G06F12/0875

    CPC classification number: G06F12/0875 ,  G06F2212/60

    Abstract: Techniques are disclosed relating to cache footprint management. In some embodiments, execution circuitry is configured to perform operations for instructions from multiple threads in parallel. Cache circuitry may store information operated on by threads executed by the execution circuitry. Scheduling circuitry may arbitrate among threads to schedule threads for execution by the execution circuitry. Tracking circuitry may determine one or more performance metrics for the cache circuitry. Control circuitry may, based on the one or more performance metrics meeting a threshold, reduce a limit on a number of threads considered for arbitration by the scheduling circuitry, to control a footprint of information stored by the cache circuitry. Disclosed techniques may advantageously reduce or avoid cache thrashing for certain processor workloads.

    Electronic Devices with Collaborative System Selection Capabilities
    8.
    发明公开
    Electronic Devices with Collaborative System Selection Capabilities 审中-公开

    公开(公告)号：US20240015495A1

    公开(公告)日：2024-01-11

    申请号：US17860704

    申请日：2022-07-08

    Applicant: Apple Inc.

    Inventor： Minghai Feng ,  Weiku Zhai ,  Tao Zeng ,  Cheng Li ,  Yaoqi Yan ,  Ying Zhang ,  Jishan Gao ,  Yong Ba ,  Ruirui Zong

    IPC: H04W8/00 ,  H04W76/10 ,  H04W48/18

    CPC classification number: H04W8/005 ,  H04W76/10 ,  H04W48/18

    Abstract: An electronic device may include wireless circuitry with first and second receivers. Each receiver may include circuitry for receiving radio-frequency signals using a first radio access technology (RAT) and using second or additional RATs. The wireless circuitry may perform system selection in which the receivers attempt to acquire a signal transmitted by a base station using different RATs. The first receiver and the second receiver may concurrently perform system selection in which the first receiver performs a band scan over the first RAT while the second receiver concurrently performs a band scan over a second or additional RAT. Additional band scans may be performed as needed until a signal is acquired. Once a signal is acquired, the wireless circuitry may establish cellular communications with the wireless base station based on the acquired signal. This may minimize the amount of time required to begin cellular telephone communications in many situations.

    Scoreboard for Register Data Cache
    9.
    发明申请
    Scoreboard for Register Data Cache 有权

    公开(公告)号：US20250103493A1

    公开(公告)日：2025-03-27

    申请号：US18410413

    申请日：2024-01-11

    Applicant: Apple Inc.

    Inventor： Winnie W. Yeung ,  Zelin Zhang ,  Cheng Li ,  Hungse Cha ,  Leela Kishore Kothamasu

    IPC: G06F12/0811 ,  G06F12/12

    Abstract: Techniques are disclosed relating to graphics processor data caches. In some embodiments, datapath executes instructions that operate on input operands from architectural registers. Data cache circuitry caches architectural register data for the datapath circuitry. Scoreboard circuitry tracks, for a given architectural register: map information that indicates whether the architectural register is mapped to an entry of the data cache circuitry and a pointer to the entry of the data cache circuitry. Tiered scoreboard circuitry and data storage circuitry may be implemented (e.g., to provide fast scoreboard access for active threads and to give a landing spot for long-latency data retrieval operations). Various disclosed techniques may improve cache performance, reduce power consumption, reduce area, or some combination thereof.

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