公开(公告)号：US20250103493A1

公开(公告)日：2025-03-27

申请号：US18410413

申请日：2024-01-11

Applicant: Apple Inc.

Inventor： Winnie W. Yeung ,  Zelin Zhang ,  Cheng Li ,  Hungse Cha ,  Leela Kishore Kothamasu

IPC: G06F12/0811 ,  G06F12/12

Abstract: Techniques are disclosed relating to graphics processor data caches. In some embodiments, datapath executes instructions that operate on input operands from architectural registers. Data cache circuitry caches architectural register data for the datapath circuitry. Scoreboard circuitry tracks, for a given architectural register: map information that indicates whether the architectural register is mapped to an entry of the data cache circuitry and a pointer to the entry of the data cache circuitry. Tiered scoreboard circuitry and data storage circuitry may be implemented (e.g., to provide fast scoreboard access for active threads and to give a landing spot for long-latency data retrieval operations). Various disclosed techniques may improve cache performance, reduce power consumption, reduce area, or some combination thereof.