公开(公告)号：EP1938168A2

公开(公告)日：2008-07-02

申请号：EP06795586.4

申请日：2006-10-06

Applicant: Axalto S.A. ,  STMicroelectronics SA

Inventor： LEYDIER, Robert ,  POMET, Alain ,  DUVAL, Benjamin

IPC: G06F1/04 ,  H03L7/197

CPC classification number: G06F1/04 ,  H03K5/133 ,  H03K5/135 ,  H03K5/156 ,  H03K2005/00058 ,  H04L7/0338

Abstract: One delay circuit is inserted in open loop inside a clock recovery circuit for improving the accuracy of clock recovery. One oscillator signal φ(0) to φ(2i-1) is provided with a basic Step of Time. A rational number of Step of Time corresponding to a bit-duration is measured inside a received flow of bits. The oscillator signal φ(0) to j(2i-1) is transformed into a clock signal CK having active edges of said clock signal in phase with at least one oscillator signal φ(0) to φ(2i-1), two consecutive active edges being separated by a time duration proportional to the integer part of the number of Step of Time. A time delay is computed proportional to the fractional part of the number of Step of Time. The next active edge of the clock signal CK is delayed of said computed delay.

公开(公告)号：WO2007042928A3

公开(公告)日：2007-04-19

申请号：PCT/IB2006/002860

申请日：2006-10-06

Applicant: AXALTO SA ,  STMicroelectronics SA ,  LEYDIER, Robert ,  POMET, Alain ,  DUVAL, Benjamin

Inventor： LEYDIER, Robert ,  POMET, Alain ,  DUVAL, Benjamin

IPC: G06F1/04 ,  H03L7/197

Abstract: One delay circuit is inserted in open loop inside a clock recovery circuit for improving the accuracy of clock recovery. One oscillator signal φ(0) to φ(2 i -1) is provided with a basic Step of Time. A rational number of Step of Time corresponding to a bit-duration is measured inside a received flow of bits. The oscillator signal φ(0) to j(2 i -1) is transformed into a clock signal CK having active edges of said clock signal in phase with at least one oscillator signal φ(0) to φ(2 i -1), two consecutive active edges being separated by a time duration proportional to the integer part of the number of Step of Time. A time delay is computed proportional to the fractional part of the number of Step of Time. The next active edge of the clock signal CK is delayed of said computed delay.