公开(公告)号：US20250063714A1

公开(公告)日：2025-02-20

申请号：US18714798

申请日：2022-12-20

Applicant: BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY

Inventor： Zhengyong ZHU ,  Chao ZHAO ,  Bokmoon KANG ,  Guilei WANG

IPC: H10B12/00 ,  H01L27/088 ,  H01L29/786

Abstract: Provided is a memory. The memory includes: a plurality of memory cells, word lines, and bit lines; wherein each of the memory cells comprises: a first transistor, wherein a first source of the first transistor is electrically connected to the bit line; a second transistor, connected in series to the first transistor; and a capacitor, electrically connected to a second drain of the second transistor. The first transistor and the second transistor are both n-type transistors or p-type transistors, and a first gate of the first transistor and a second gate of the second transistor are electrically connected to the word line.

公开(公告)号：US20250029653A1

公开(公告)日：2025-01-23

申请号：US18714879

申请日：2022-05-12

Applicant: BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY

Inventor： Zhengyong ZHU ,  Bokmoon KANG ,  Dan WANG ,  Chao ZHAO

IPC: G11C11/4096 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4094

Abstract: Provided is a memory. The memory includes at least one memory array and at least one control circuit, wherein the memory array comprises a plurality of memory cells arranged in an array as well as read wordlines and read bitlines for read operations, wherein each of the memory cells comprises a first transistor and a second transistor. The control circuit is configured to transmit, during a pre-processing stage, a first voltage to the read wordline and the read bitline; transmit, during a pre-charging stage, a second voltage to the read bitline; and transmit, during a read-sensing stage, a third voltage to the read wordline.