公开(公告)号：US20250031411A1

公开(公告)日：2025-01-23

申请号：US18714965

申请日：2022-12-07

Applicant: BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY

Inventor： Huihui LI ,  Yunsen ZHANG ,  Guilei WANG ,  Chao ZHAO

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H10B12/00 ,  H10B61/00

Abstract: A vertical transistor, and a memory cell and a manufacturing method therefor are provided. The vertical transistor includes: a source electrode disposed on a substrate; a drain electrode which is disposed at a side, away from the substrate, of the source electrode; and a gate electrode and a semiconductor layer, which are in the same layer, and are disposed between the source electrode and the drain electrode in a first direction which is perpendicular to the substrate. The gate electrode at least comprises a column-shaped first gate electrode extending in the first direction. The semiconductor layer comprises a first semiconductor layer and a second semiconductor layer which are in the same layer and spaced apart from each other, and the first gate electrode is disposed between the first semiconductor layer and the second semiconductor layer.

公开(公告)号：US20240381626A1

公开(公告)日：2024-11-14

申请号：US18695254

申请日：2023-08-21

Applicant: BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY

Inventor： Xuezheng AI ,  Xiangsheng WANG ,  Guilei WANG ,  Chao ZHAO ,  Jin DAI ,  Wenhua GUI

IPC: H10B12/00

Abstract: Disclosed is a memory, a method for manufacturing the memory. The memory includes: one or more layers of memory cell arrays stacked in a direction perpendicular to a substrate; a plurality of wordlines that penetrate through one or more layers of the memory cell arrays; and a plurality of bitlines, wherein each memory cell includes a semiconductor layer that surrounds a sidewall of the wordline and extends along the sidewall and each bitline is connected to the semiconductor layers of a column of memory cells in one layer of the memory cell array, wherein the bitline is composed of different branch lines, and the semiconductor layer of each memory cell is connected to two adjacent first branch lines but is not connected to at least a part of the region of the second branch line between the two adjacent first branch lines.

公开(公告)号：US20250071968A1

公开(公告)日：2025-02-27

申请号：US18754367

申请日：2024-06-26

Applicant: BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY

Inventor： Xuezheng AI ,  Xiangsheng WANG ,  Guilei WANG ,  Chao ZHAO ,  Wenhua GUI

IPC: H01L23/528 ,  H01L23/522 ,  H10B12/00

Abstract: A semiconductor device, manufacturing method therefor, and electronic equipment are provided. The manufacturing method includes: alternately depositing sacrificial layers and insulation layers to obtain a stacked structure; forming in the stacked structure a plurality of via holes distributed at intervals, and forming dummy word lines in the via holes; forming a first trench penetrating through the stacked structure every two via holes apart; forming a plurality of grooves by re-etching the plurality of insulation layers within the first trench, wherein two grooves of each insulation layer in two first trenches respectively expose partial side walls of a dummy word line; forming conductive layers within the two grooves corresponding to each insulation layer, wherein a conductive layer within each groove surrounds two exposed dummy word lines; and disconnecting a conductive layer surrounding a dummy word line to form a first electrode and a second electrode of a transistor.

公开(公告)号：US20250063714A1

公开(公告)日：2025-02-20

申请号：US18714798

申请日：2022-12-20

Applicant: BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY

Inventor： Zhengyong ZHU ,  Chao ZHAO ,  Bokmoon KANG ,  Guilei WANG

IPC: H10B12/00 ,  H01L27/088 ,  H01L29/786

Abstract: Provided is a memory. The memory includes: a plurality of memory cells, word lines, and bit lines; wherein each of the memory cells comprises: a first transistor, wherein a first source of the first transistor is electrically connected to the bit line; a second transistor, connected in series to the first transistor; and a capacitor, electrically connected to a second drain of the second transistor. The first transistor and the second transistor are both n-type transistors or p-type transistors, and a first gate of the first transistor and a second gate of the second transistor are electrically connected to the word line.

公开(公告)号：US20250029653A1

公开(公告)日：2025-01-23

申请号：US18714879

申请日：2022-05-12

Applicant: BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY

Inventor： Zhengyong ZHU ,  Bokmoon KANG ,  Dan WANG ,  Chao ZHAO

IPC: G11C11/4096 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4094

Abstract: Provided is a memory. The memory includes at least one memory array and at least one control circuit, wherein the memory array comprises a plurality of memory cells arranged in an array as well as read wordlines and read bitlines for read operations, wherein each of the memory cells comprises a first transistor and a second transistor. The control circuit is configured to transmit, during a pre-processing stage, a first voltage to the read wordline and the read bitline; transmit, during a pre-charging stage, a second voltage to the read bitline; and transmit, during a read-sensing stage, a third voltage to the read wordline.