公开(公告)号：EP4394772A1

公开(公告)日：2024-07-03

申请号：EP22934532.7

申请日：2022-06-08

Applicant: Beijing Superstring Academy of Memory Technology

Inventor： ZHU, Zhengyong ,  KANG, Bokmoon ,  WANG, Guilei ,  ZHAO, Chao

IPC: G11C11/407

Abstract: Embodiments of the present invention provide a memory and a manufacturing method therefor, and an electronic device. The memory comprises a substrate, and a word line, a bit line and a storage unit on one side of the substrate. The storage unit comprises a transistor. The transistor comprises: a semiconductor layer which comprises a source contact region, a semiconductor region, and a drain contact region which are sequentially connected; a main gate electrically connected to the word line; a source electrically connected to the bit line and the source contact region of the semiconductor layer, respectively; a drain electrically connected to the drain contact region of the semiconductor layer; and a secondary gate electrically connected to the drain. The orthographic projection of the main gate on the substrate and the orthographic projection of the secondary gate on the substrate at least partially overlap with the orthographic projection of the semiconductor region of the semiconductor layer on the substrate. According to the present invention, on the basis that the transistor has the main gate, the secondary gate electrically connected to the drain is introduced, the secondary gate can obtain a fixed potential synchronous with the drain, and provide supplement control for the semiconductor layer by utilizing the fixed potential, thereby optimizing the read-write performance of the memory.

公开(公告)号：EP4395490A1

公开(公告)日：2024-07-03

申请号：EP22934524.4

申请日：2022-06-02

Applicant: Beijing Superstring Academy of Memory Technology

Inventor： ZHU, Zhengyong ,  KANG, Bokmoon ,  WANG, Guilei ,  ZHAO, Chao

IPC: H10B12/00

Abstract: A semiconductor memory device (10) and a manufacturing method and a read/write method therefor, and an electronic device and a memory circuit. A transistor (11) is arranged in each memory unit (101) in the semiconductor memory device (10), wherein a gate electrode (115) and a secondary electrode (116) are arranged in the transistor (11), and the secondary electrode (116) is electrically connected to a drain electrode (112). When a write operation is performed, a first voltage is applied to the gate electrode (115) by means of a word line (31), and an electrical signal is then applied to a source electrode (113) by means of a bit line (32) and according to external input data; and when a read operation is performed, by using the effect of a voltage of the secondary electrode (116) on a threshold voltage of the transistor (11), a second voltage is applied to the secondary electrode (116) by means of the word line (31), and the magnitude of the second voltage is between a threshold voltage of when the transistor (11) stores "1" and a threshold voltage of when the transistor (11) stores "0", and data is then read by means of detecting the magnitude of an output current of a field effect transistor.