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    2.
    发明专利
    未知

    公开(公告)号：DE69129523D1

    公开(公告)日：1998-07-09

    申请号：DE69129523

    申请日：1991-09-17

    Applicant: CANON KK

    Inventor： OZAWA KUNITAKA ,  KADOSAWA TSUNEAKI ,  NAKAMURA TAKASHI ,  KOGA EIJI ,  WATANABE HITOSHI

    IPC: G06F9/46 ,  G06F9/48

    Abstract: An information processing system having a memory for storing a plurality of programs executed in a parallel processing manner, an instruction interpretation section for interpreting instructions in the programs, and an instruction execution section for executing the interpreted instructions. Cues for registering the numbers of the steps of the programs to be executed, wherein the numbers of the steps to be executed next are registered in the cues, the number of each step registered in the cues is read out, the processing to be performed in accordance with the step corresponding to the step number read out is interpreted, and instructions are given to the instruction interpretation section according to the content of the step interpreted. The step numbers of other steps to be executed are registered in the cues, and the plurality of programs are executed in parallel based on the order of the cues.

    5.
    发明专利
    未知

    公开(公告)号：DE69327551D1

    公开(公告)日：2000-02-17

    申请号：DE69327551

    申请日：1993-06-29

    Applicant: CANON KK

    Inventor： WATANABE HITOSHI ,  KADOSAWA TSUNEAKI ,  NAKAMURA TAKASHI ,  KOGA EIJI ,  ASADA SATOSHI

    IPC: G06F11/28 ,  G06F11/36 ,  G06F11/00

    Abstract: In a method for executing a program for sequentially reading step information registered in an execution queue in the order of registration in order to permit the modification of a branch-to address with ease and without error when the modification of the branch-to address is instructed during the debugging of the program, the step information which is no longer the branch-to address due to the modification is searched in response to the branch-to address modification instruction, the retrieved step information is erased from the execution queue, and step information which is a new branch-to address is registered at the position of the erased step.

    6.
    发明专利
    未知

    公开(公告)号：DE69129962D1

    公开(公告)日：1998-09-17

    申请号：DE69129962

    申请日：1991-10-07

    Applicant: CANON KK

    Inventor： NAKAMURA TAKASHI ,  OZAWA KUNITAKA ,  KADOSAWA TSUNEAKI ,  KOGA EIJI ,  WATANABE HITOSHI

    IPC: G06F15/16 ,  G06F15/17 ,  G06F15/177

    Abstract: An information processor including a plurality of processors interconnected by communication means, each processor having a memory storing a program and data, an instruction interpretation section for interpreting instructions in the program, and an instruction execution section for executing the result of interpretation. Each processor referring to the address of source data or destination data indicated by an operand of a data transfer instruction, and determining which of the plurality of processors the source data or destination data pertain.

    7.
    发明专利
    未知

    公开(公告)号：DE69327551T2

    公开(公告)日：2000-05-25

    申请号：DE69327551

    申请日：1993-06-29

    Applicant: CANON KK

    Inventor： WATANABE HITOSHI ,  KADOSAWA TSUNEAKI ,  NAKAMURA TAKASHI ,  KOGA EIJI ,  ASADA SATOSHI

    IPC: G06F11/28 ,  G06F11/36 ,  G06F11/00

    Abstract: In a method for executing a program for sequentially reading step information registered in an execution queue in the order of registration in order to permit the modification of a branch-to address with ease and without error when the modification of the branch-to address is instructed during the debugging of the program, the step information which is no longer the branch-to address due to the modification is searched in response to the branch-to address modification instruction, the retrieved step information is erased from the execution queue, and step information which is a new branch-to address is registered at the position of the erased step.

    9.
    发明专利
    未知

    公开(公告)号：DE69129962T2

    公开(公告)日：1999-01-14

    申请号：DE69129962

    申请日：1991-10-07

    Applicant: CANON KK

    Inventor： NAKAMURA TAKASHI ,  OZAWA KUNITAKA ,  KADOSAWA TSUNEAKI ,  KOGA EIJI ,  WATANABE HITOSHI

    IPC: G06F15/16 ,  G06F15/17 ,  G06F15/177

    Abstract: An information processor including a plurality of processors interconnected by communication means, each processor having a memory storing a program and data, an instruction interpretation section for interpreting instructions in the program, and an instruction execution section for executing the result of interpretation. Each processor referring to the address of source data or destination data indicated by an operand of a data transfer instruction, and determining which of the plurality of processors the source data or destination data pertain.

    10.
    发明专利
    未知

    公开(公告)号：DE69129523T2

    公开(公告)日：1998-11-26

    申请号：DE69129523

    申请日：1991-09-17

    Applicant: CANON KK

    Inventor： OZAWA KUNITAKA ,  KADOSAWA TSUNEAKI ,  NAKAMURA TAKASHI ,  KOGA EIJI ,  WATANABE HITOSHI

    IPC: G06F9/46 ,  G06F9/48

    Abstract: An information processing system having a memory for storing a plurality of programs executed in a parallel processing manner, an instruction interpretation section for interpreting instructions in the programs, and an instruction execution section for executing the interpreted instructions. Cues for registering the numbers of the steps of the programs to be executed, wherein the numbers of the steps to be executed next are registered in the cues, the number of each step registered in the cues is read out, the processing to be performed in accordance with the step corresponding to the step number read out is interpreted, and instructions are given to the instruction interpretation section according to the content of the step interpreted. The step numbers of other steps to be executed are registered in the cues, and the plurality of programs are executed in parallel based on the order of the cues.

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