公开(公告)号：WO1998029945A1

公开(公告)日：1998-07-09

申请号：PCT/US1997024128

申请日：1997-12-30

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  BEZZANT, Daniel, G. ,  CARCHOT, Joseph ,  RAMPRASAD, Rangarajan ,  SHETTY, Nagina, Naresh

IPC: H03K03/86

CPC classification number: H03K5/135 ,  H03K5/00006

Abstract: A clock frequency multiplier with a rise detector flip-flop connected to a series of buffers having interspersed parallel output taps connected to a binary to Gray converter for providing real time rise status indications. The parallel tap outputs are connected to first, second and third multiplexers, to produce first and second fall outputs and a second rise output. The multiplexers are controlled by first, second and third corresponding tap circuits having hexadecimal inputs from a Gray to hexadecimal converter connected to the output of the binary to Gray converter through a flip-flop clocked by a second rise of the input clock signal.

Abstract translation: 具有连接到一系列缓冲器的上升检测器触发器的时钟倍增器，其具有连接到二进制到灰度转换器的散布的并行输出抽头，用于提供实时上升状态指示。 并联抽头输出连接到第一，第二和第三复用器，以产生第一和第二下降输出和第二上升输出。 多路复用器由具有从灰度到十六进制转换器的十六进制输入的第一，第二和第三对应分接电路控制，所述十六进制输入通过由输入时钟信号的第二个上升时钟的触发器连接到二进制到格雷转换器的输出。