公开(公告)号：JPH1092119A

公开(公告)日：1998-04-10

申请号：JP10641097

申请日：1997-04-23

Applicant: CIRRUS LOGIC INC

Inventor： BLISS WILLIAM G ,  BEHRENS RICHARD T ,  DU LI ,  REED DAVID ,  SPURBECK MARK

IPC: G11B5/09 ,  G11B20/10 ,  G11B20/12 ,  G11B20/14 ,  G11B20/18 ,  H03H15/00 ,  H03H17/00 ,  H03H17/06 ,  H04L25/03

Abstract: PROBLEM TO BE SOLVED: To realize a discrete time filter of a high order and an analog filter of a lower order by using a sampling read channel which is provided with a sampling device, with an adaptive equalizer, with an interpolated timing recovery and with a discrete time sequence detector. SOLUTION: In a sampled amplitude read channel, an interpolated timing recovery B100 is provided instead of a conventional sampled timing recovery. In addition, a write frequency synthesizer 52 generates a baud rate clock 54 which is given to a write circuit 9. A sampling device 24, a discrete time equalizer filter B103 and the interpolated timing recovery B100 generate the asynchronous read clock 54 which is clock-matched at a frequency CDR 30 with reference to a present zone.