公开(公告)号：JPH1092118A

公开(公告)日：1998-04-10

申请号：JP10640997

申请日：1997-04-23

Applicant: CIRRUS LOGIC INC

Inventor： SPURBECK MARK S ,  DU LI ,  TRENT DUDLEY O ,  BLISS WILLIAM G ,  FEYH GERMAN S ,  BEHRENS RICHARD T

IPC: G11B5/012 ,  G11B5/035 ,  G11B5/09 ,  G11B20/10 ,  G11B20/14 ,  G11B20/18 ,  H03H15/00 ,  H03H17/02 ,  H03H17/06 ,  H04L7/00 ,  H04L7/02 ,  H04L25/03

Abstract: PROBLEM TO BE SOLVED: To realize a discrete time filter of a higher order and an analog filter of a lower order by using a sampling read channel which is provided with a sampling device, with an adaptive equalizer, with a restriction circuit and with a discrete time sequence detector. SOLUTION: In a sampled amplitude read channel, an interpolated timing recovery B100 is provided instead of a conventional sampling timing recovery. In addition, a write frequency synthesizer 52 generates a baut rate write clock 54 which is given to a write circuit 9. A sampling device 24, a discrete time equalizer filter B103 and the interpolated timing recovery B100 generate an asynchronous read clock 54 which is clock-matched at a frequency CDR 30 with reference to a present zone.

公开(公告)号：JPH1092119A

公开(公告)日：1998-04-10

申请号：JP10641097

申请日：1997-04-23

Applicant: CIRRUS LOGIC INC

Inventor： BLISS WILLIAM G ,  BEHRENS RICHARD T ,  DU LI ,  REED DAVID ,  SPURBECK MARK

IPC: G11B5/09 ,  G11B20/10 ,  G11B20/12 ,  G11B20/14 ,  G11B20/18 ,  H03H15/00 ,  H03H17/00 ,  H03H17/06 ,  H04L25/03

Abstract: PROBLEM TO BE SOLVED: To realize a discrete time filter of a high order and an analog filter of a lower order by using a sampling read channel which is provided with a sampling device, with an adaptive equalizer, with an interpolated timing recovery and with a discrete time sequence detector. SOLUTION: In a sampled amplitude read channel, an interpolated timing recovery B100 is provided instead of a conventional sampled timing recovery. In addition, a write frequency synthesizer 52 generates a baud rate clock 54 which is given to a write circuit 9. A sampling device 24, a discrete time equalizer filter B103 and the interpolated timing recovery B100 generate the asynchronous read clock 54 which is clock-matched at a frequency CDR 30 with reference to a present zone.

公开(公告)号：WO0247083A3

公开(公告)日：2003-09-12

申请号：PCT/US0144999

申请日：2001-11-30

Applicant: CIRRUS LOGIC INC

Inventor： REED DAVID E ,  TURK STEPHEN A ,  DU LI

IPC: G11B5/55 ,  G11B5/596 ,  G11B20/10 ,  G11B20/18 ,  G11B21/08 ,  G11B21/10 ,  G11B5/09 ,  G11B20/14

CPC classification number: G11B5/5543 ,  G11B5/59633 ,  G11B20/10 ,  G11B20/1833

Abstract: Servo circuitry (325) is disclosed that is configured to operate with a magnetic disk drive system. The servo circuitry is comprised of a first servo detector system (401), a second servo detector system (402), and a comparator (416). The first servo detector system and the second servo detector system each receive samples, taken from a read signal, that include servo data. The first servo detector system compares the samples to a plurality of servo codes to generate a first selected code. The second servo detector system compares a first shifted version of the samples to the plurality of servo codes to generate a second selected code. The comparator receives the selected codes and selects one of the selected codes. The selected code represents the servo data (359). The servo circuitry could also include a third servo detector system (403) that operates on a second shifted version of the samples. Alternatively, the first servo detector system, the second servo detector system, and the third servo detector system could each be programmed with different servo codes. The first servo detector system compares the samples to a plurality of first servo codes. The second servo detector system compares the samples to a plurality of second servo codes. The third servo detector system compares the samples to a plurality of third servo codes. The second servo codes and the third servo codes are shifted versions of the first servo codes. In either embodiment, the servo circuitry advantageously has improved phase shift tolerance.

Abstract translation: 公开了配置成与磁盘驱动系统一起操作的伺服电路（325）。 伺服电路包括第一伺服检测器系统（401），第二伺服检测器系统（402）和比较器（416）。 第一伺服检测器系统和第二伺服检测器系统每个从包括伺服数据的读取信号中接收采样。 第一伺服检测器系统将样本与多个伺服码进行比较以产生第一选择的码。 第二伺服检测器系统将样本的第一移位版本与多个伺服码进行比较，以产生第二选择的码。 比较器接收所选择的代码并选择所选代码之一。 选择的代码表示伺服数据（359）。 伺服电路还可以包括在样本的第二移位版本上操作的第三伺服检测器系统（403）。 或者，第一伺服检测器系统，第二伺服检测器系统和第三伺服检测器系统可以各自用不同的伺服代码进行编程。 第一伺服检测器系统将样本与多个第一伺服码进行比较。 第二伺服检测器系统将样本与多个第二伺服码进行比较。 第三伺服检测器系统将样本与多个第三伺服码进行比较。 第二伺服码和第三伺服码是第一伺服码的移位版本。 在任一实施例中，伺服电路有利地具有改进的相移公差。