公开(公告)号：JPH10283743A

公开(公告)日：1998-10-23

申请号：JP1625198

申请日：1998-01-28

Applicant: CIRRUS LOGIC INC

Inventor： RICHARD T BEHRENS ,  ZOOK CHRISTOPHER P ,  STEVEN A TARKE ,  REED DAVID E

IPC: G11B5/55 ,  G11B5/596 ,  G11B7/007 ,  G11B21/08 ,  G11B21/10 ,  G11B27/30

Abstract: PROBLEM TO BE SOLVED: To enable a servo code format for a high recording density by mapping the detected code word of adjacent tracks to the decoded code word indicating one adjacent track at the time of mapping two detected code words to one decoded code word to seek the selected track with a read head. SOLUTION: This decoder 84 performs the decoding to an effective track address of estimated data sequence even when a readout signal becomes ambiguous due to interference between tracks during the seek operation. That is, a binary track address is coded depending on the coding scheme for correcting random bit error and ambiguity generated as a result of interference between tracks during the seek operation can be solved to overcome the limitation on the servo gray code. After the correction, seven code word bits is mapped to the four information bits in order to decode the code word.

公开(公告)号：JPH1069727A

公开(公告)日：1998-03-10

申请号：JP18559597

申请日：1997-07-10

Applicant: CIRRUS LOGIC INC

Inventor： FOLAND WILLIAM R JR ,  SUNDELL LISA C ,  REED DAVID E ,  BLISS WILLIAM G ,  BEHRENS RICHARD T

IPC: G11B20/10 ,  G11B20/14 ,  G11B20/18 ,  G11B19/02

Abstract: PROBLEM TO BE SOLVED: To operate a sampled amplitude lead channel for a computer storage system at a high user data rate and density by providing with a sampling value generating and detecting device. SOLUTION: User data 2 or pre-amp data from a data generator 4 are written on a medium during a write operation. User data 2 are coded into a binary sequence b(n)8 with a RLL encoder 6. The transfer function of a recording channel 18 and equalizer filter are compensated, and the binary sequence b(n)8 is pre-coded in order to make a pre-coded sequence b(n)12 and converted into a symbol a(n)16 with a pre-coder 10. Also, an analog lead signal 62 from an analog receiving filter 20 is sampled with a sampling device (A/D) 24, and the sampling value 25 is further equalized in order to obtain a desired response with a discrete-time equalizer filter 26.

公开(公告)号：DE69620354D1

公开(公告)日：2002-05-08

申请号：DE69620354

申请日：1996-12-02

Applicant: CIRRUS LOGIC INC

Inventor： REED DAVID E ,  BLISS WILLIAM G

IPC: G11B5/596 ,  G11B5/09 ,  G11B20/10 ,  G11B20/12 ,  G11B20/14 ,  G11B21/10 ,  H04L7/02 ,  G11B5/02 ,  G11B20/08

Abstract: A sampled amplitude read channel reads user data and embedded servo data stored on a magnetic medium by detecting digital data from a sequence of discrete time interpolated sample values. A write frequency synthesizer generates a write clock for writing digital data to the magnetic medium at a predetermined baud rate for a selected zone, and upon read back, a read frequency synthesizer generates a fixed sampling clock at a frequency slightly higher than the write frequency at the outer zone. A sampling device samples the analog read signal at this fixed sampling rate across the data zones and servo wedges to generate a sequence of discrete time channel samples that are not synchronized to the baud rate. Before sampling, an analog receive filter processes the read signal to attenuate aliasing noise without having to adjust its spectrum across data zones or servo wedges. A discrete time equalizing filter equalizes the channel samples according to a predetermined partial response (PR4, EPR4, EEPR4, etc.). An interpolating timing recovery circuit, responsive to the equalized channel samples, computes an interpolation interval tau and, in response thereto, generates interpolated sample values substantially synchronized to the baud rate. The timing recovery circuit also generates a synchronous data clock for clocking a discrete time sequence detector and pulse detector which detect the digital user and servo data from the interpolated sample values.

公开(公告)号：US5668678B1

公开(公告)日：2000-11-28

申请号：US32584294

申请日：1994-11-14

Applicant: CIRRUS LOGIC INC

Inventor： REED DAVID E ,  BEHERNS RICHARD T ,  BLISS WILLIAM G

IPC: G11B5/596 ,  G11B21/08 ,  G11B21/10 ,  G11B5/09

CPC classification number: G11B21/083 ,  G11B5/59655 ,  G11B5/59688 ,  G11B20/10037 ,  G11B20/10055 ,  G11B21/085 ,  G11B21/106

公开(公告)号：DE69620354T2

公开(公告)日：2002-11-21

申请号：DE69620354

申请日：1996-12-02

Applicant: CIRRUS LOGIC INC

Inventor： REED DAVID E ,  BLISS WILLIAM G

IPC: G11B5/596 ,  G11B5/09 ,  G11B20/10 ,  G11B20/12 ,  G11B20/14 ,  G11B21/10 ,  H04L7/02 ,  G11B5/02 ,  G11B20/08

Abstract: A sampled amplitude read channel reads user data and embedded servo data stored on a magnetic medium by detecting digital data from a sequence of discrete time interpolated sample values. A write frequency synthesizer generates a write clock for writing digital data to the magnetic medium at a predetermined baud rate for a selected zone, and upon read back, a read frequency synthesizer generates a fixed sampling clock at a frequency slightly higher than the write frequency at the outer zone. A sampling device samples the analog read signal at this fixed sampling rate across the data zones and servo wedges to generate a sequence of discrete time channel samples that are not synchronized to the baud rate. Before sampling, an analog receive filter processes the read signal to attenuate aliasing noise without having to adjust its spectrum across data zones or servo wedges. A discrete time equalizing filter equalizes the channel samples according to a predetermined partial response (PR4, EPR4, EEPR4, etc.). An interpolating timing recovery circuit, responsive to the equalized channel samples, computes an interpolation interval tau and, in response thereto, generates interpolated sample values substantially synchronized to the baud rate. The timing recovery circuit also generates a synchronous data clock for clocking a discrete time sequence detector and pulse detector which detect the digital user and servo data from the interpolated sample values.

公开(公告)号：WO0247083A3

公开(公告)日：2003-09-12

申请号：PCT/US0144999

申请日：2001-11-30

Applicant: CIRRUS LOGIC INC

Inventor： REED DAVID E ,  TURK STEPHEN A ,  DU LI

IPC: G11B5/55 ,  G11B5/596 ,  G11B20/10 ,  G11B20/18 ,  G11B21/08 ,  G11B21/10 ,  G11B5/09 ,  G11B20/14

CPC classification number: G11B5/5543 ,  G11B5/59633 ,  G11B20/10 ,  G11B20/1833

Abstract: Servo circuitry (325) is disclosed that is configured to operate with a magnetic disk drive system. The servo circuitry is comprised of a first servo detector system (401), a second servo detector system (402), and a comparator (416). The first servo detector system and the second servo detector system each receive samples, taken from a read signal, that include servo data. The first servo detector system compares the samples to a plurality of servo codes to generate a first selected code. The second servo detector system compares a first shifted version of the samples to the plurality of servo codes to generate a second selected code. The comparator receives the selected codes and selects one of the selected codes. The selected code represents the servo data (359). The servo circuitry could also include a third servo detector system (403) that operates on a second shifted version of the samples. Alternatively, the first servo detector system, the second servo detector system, and the third servo detector system could each be programmed with different servo codes. The first servo detector system compares the samples to a plurality of first servo codes. The second servo detector system compares the samples to a plurality of second servo codes. The third servo detector system compares the samples to a plurality of third servo codes. The second servo codes and the third servo codes are shifted versions of the first servo codes. In either embodiment, the servo circuitry advantageously has improved phase shift tolerance.

Abstract translation: 公开了配置成与磁盘驱动系统一起操作的伺服电路（325）。 伺服电路包括第一伺服检测器系统（401），第二伺服检测器系统（402）和比较器（416）。 第一伺服检测器系统和第二伺服检测器系统每个从包括伺服数据的读取信号中接收采样。 第一伺服检测器系统将样本与多个伺服码进行比较以产生第一选择的码。 第二伺服检测器系统将样本的第一移位版本与多个伺服码进行比较，以产生第二选择的码。 比较器接收所选择的代码并选择所选代码之一。 选择的代码表示伺服数据（359）。 伺服电路还可以包括在样本的第二移位版本上操作的第三伺服检测器系统（403）。 或者，第一伺服检测器系统，第二伺服检测器系统和第三伺服检测器系统可以各自用不同的伺服代码进行编程。 第一伺服检测器系统将样本与多个第一伺服码进行比较。 第二伺服检测器系统将样本与多个第二伺服码进行比较。 第三伺服检测器系统将样本与多个第三伺服码进行比较。 第二伺服码和第三伺服码是第一伺服码的移位版本。 在任一实施例中，伺服电路有利地具有改进的相移公差。

公开(公告)号：AU9038498A

公开(公告)日：1999-04-27

申请号：AU9038498

申请日：1998-08-28

Applicant: CIRRUS LOGIC INC

Inventor： REED DAVID E ,  BLISS WILLIAM G ,  FEYH GERMAN S

IPC: G11B5/012 ,  G11B5/02 ,  G11B5/09 ,  G11B20/10 ,  G11B20/24 ,  G11B27/36 ,  G11B20/22

Abstract: A thermal asperity-tolerant read channel is provided for a magnetic disk drive. Thermal asperities are detected by a digital detector which includes a pre-filter, a first threshold comparator and, optionally, a second threshold comparator. The pre-filter reduces noise and signal variation in the analog-to-digital converter output to enable better detection of a DC shift caused by a thermal asperity. The first threshold comparator compares the pre-filter output to a predetermined level; if the predetermined level is exceeded, the comparator output is set to one state, providing an initial indication of the presence of a thermal asperity. The optional second threshold comparator determines whether, out of a predetermined number of comparator outputs, the number in the one state exceeds programmed value; if so, the second threshold comparator outputs a final indication of the presence of a thermal asperity. In such a manner, accurate detection of thermal asperities is enhanced while reducing the likelihood of false detection. When a thermal asperity is detected, one or more of the following features can be activated to reduce the adverse effects of the thermal asperity: a squelch connected to the inputs of the variable gain amplifier; a loop-hold feature to maintain channel parameters such as timing, offset and gain until the effects of the thermal asperity have dissipated; and a user data erasure pointer to flag data which has been corrupted by the thermal asperity and which needs to be corrected by ECC circuitry.

公开(公告)号：EP0777211A3

公开(公告)日：1998-08-19

申请号：EP96119296

申请日：1996-12-02

Applicant: CIRRUS LOGIC INC

Inventor： REED DAVID E ,  BLISS WILLIAM G

IPC: G11B5/596 ,  G11B5/09 ,  G11B20/10 ,  G11B20/12 ,  G11B20/14 ,  G11B21/10 ,  H04L7/02 ,  G11B5/02 ,  G11B20/08

CPC classification number: H04L7/0029 ,  G11B5/09 ,  G11B20/10009 ,  G11B20/10037 ,  G11B20/10055 ,  G11B20/10064 ,  G11B20/10074 ,  G11B20/1258 ,  G11B20/1403 ,  G11B2020/10888 ,  G11B2020/1234 ,  G11B2020/1282 ,  H04L7/0004 ,  H04L7/0062 ,  H04L2007/047

Abstract: A sampled amplitude read channel reads user data and embedded servo data stored on a magnetic medium by detecting digital data from a sequence of discrete time interpolated sample values. A write frequency synthesizer generates a write clock for writing digital data to the magnetic medium at a predetermined baud rate for a selected zone, and upon read back, a read frequency synthesizer generates a fixed sampling clock at a frequency slightly higher than the write frequency at the outer zone. A sampling device samples the analog read signal at this fixed sampling rate across the data zones and servo wedges to generate a sequence of discrete time channel samples that are not synchronized to the baud rate. Before sampling, an analog receive filter processes the read signal to attenuate aliasing noise without having to adjust its spectrum across data zones or servo wedges. A discrete time equalizing filter equalizes the channel samples according to a predetermined partial response (PR4, EPR4, EEPR4, etc.). An interpolating timing recovery circuit, responsive to the equalized channel samples, computes an interpolation interval τ and, in response thereto, generates interpolated sample values substantially synchronized to the baud rate. The timing recovery circuit also generates a synchronous data clock for clocking a discrete time sequence detector and pulse detector which detect the digital user and servo data from the interpolated sample values.