公开(公告)号：JPH1063866A

公开(公告)日：1998-03-06

申请号：JP17233097

申请日：1997-06-27

Applicant: CIRRUS LOGIC INC

Inventor： LARSON MICHAEL KERRY ,  WILDE DANIEL P

IPC: G06T11/20 ,  G06T15/80 ,  G06T11/00 ,  G06T15/00

Abstract: PROBLEM TO BE SOLVED: To make logic simple and enable fast interpolation by providing a polygon state machine which loads and selects initial values as to a 1st and a 2nd accumulator and a counter and increases the 1st and 2nd accumulators and counter. SOLUTION: The polygon state machine 350 asserts an LD signal and a MAIN signal and then starts polygon rendering operation. Multiplexers 315 and 365 select initial main values in response and they are loaded to the counter 320 and accumulators 340 and 360 together with the initial values. Then an increment signal is generated by the machine 350 and COUNT0 is counted down to zero. Each time an increment is given, an X value and a width value are generated by the accumulators 340 and 360 as to each scan line in the upper half of the polygon. When COUNT0 reaches zero, a COUNT1 value is inspected.