公开(公告)号：US3624606A

公开(公告)日：1971-11-30

申请号：US3624606D

申请日：1969-12-12

Applicant: CIT ALCATEL

Inventor： LEFEVRE ROGER

IPC: G06K9/40 ,  G06K9/12

CPC classification number: G06K9/40

Abstract: The information contained in the memory passes through an assembly of windows corresponding to various positionings, and a counter associated with each window counts the sequences of identical valences seen through each window. The result is the validation of the direction which enables the validation of the contents of a division receiving an interference signal, seen through a correction window parallel to the validated direction.

公开(公告)号：DE2111232A1

公开(公告)日：1972-09-14

申请号：DE2111232

申请日：1971-03-09

Applicant: CIT ALCATEL

Inventor： LEFEVRE ROGER

IPC: G06K9/40 ,  H04L1/02 ,  H04N1/409 ,  G06F11/00

Abstract: 1278392 Digital transmission systems; majority decision sampling COMPAGNIE INDUSTRIELLE DES TELECOMMUNICATIONS CIT-ALCATEL 18 Feb 1971 4921/71 Heading H4P In an apparatus for sampling, by majority decision, signals presented in terms of a matrix array with Q lines which are divided into perpendicular zones of h bits per line with the probability p of an erroneous bit, a first shift register 12 with h positions receives the signals sequentially which are parallelly transferred at determined intervals into a buffer memory 14 of capacity nhQ bits, with an array of n cascaded shift registers 14 each having h divisions with a majority decision circuit 15 sampling the output bits of each register. The arrangement transfers at least parts of the buffer memory content at determined intervals through register 12 to register 14 for presentation to the majority decision circuit. A television frame 10 with Q lines and vertical zones each of h bits has signals from each zone presented successively to a threshold circuit 11 which classifies signals above or below a determined blackness into digital signals of opposed type which are fed to input A of shift register 12 and transferred at determined intervals through memory 13 to the array of shift registers 14a-14n, the output bits from which are sampled and passed to 16 which provides a corrected video signal. Buffer memory 13 is preferably a circulating memory with a transfer circuit 19 having h divisions transferring content of register 12 to the input of circulating memory 21 which is suitably a delay line, hence the original group h may be retransferred after a delay into register 12 and passed into array 14. Memory 21 may circulate the data for example five times.

公开(公告)号：GB1278392A

公开(公告)日：1972-06-21

申请号：GB492171

申请日：1971-02-18

Applicant: CIT ALCATEL

Inventor： LEFEVRE ROGER

IPC: G06K9/40 ,  H04L1/02 ,  H04N1/409

Abstract: 1278392 Digital transmission systems; majority decision sampling COMPAGNIE INDUSTRIELLE DES TELECOMMUNICATIONS CIT-ALCATEL 18 Feb 1971 4921/71 Heading H4P In an apparatus for sampling, by majority decision, signals presented in terms of a matrix array with Q lines which are divided into perpendicular zones of h bits per line with the probability p of an erroneous bit, a first shift register 12 with h positions receives the signals sequentially which are parallelly transferred at determined intervals into a buffer memory 14 of capacity nhQ bits, with an array of n cascaded shift registers 14 each having h divisions with a majority decision circuit 15 sampling the output bits of each register. The arrangement transfers at least parts of the buffer memory content at determined intervals through register 12 to register 14 for presentation to the majority decision circuit. A television frame 10 with Q lines and vertical zones each of h bits has signals from each zone presented successively to a threshold circuit 11 which classifies signals above or below a determined blackness into digital signals of opposed type which are fed to input A of shift register 12 and transferred at determined intervals through memory 13 to the array of shift registers 14a-14n, the output bits from which are sampled and passed to 16 which provides a corrected video signal. Buffer memory 13 is preferably a circulating memory with a transfer circuit 19 having h divisions transferring content of register 12 to the input of circulating memory 21 which is suitably a delay line, hence the original group h may be retransferred after a delay into register 12 and passed into array 14. Memory 21 may circulate the data for example five times.