公开(公告)号：US3514697A

公开(公告)日：1970-05-26

申请号：US3514697D

申请日：1967-03-27

Applicant: CIT ALCATEL

Inventor： OSWALD JACQUES

IPC: H03M1/00 ,  H04L27/156 ,  G01R23/02

CPC classification number: H04L27/1566 ,  H03M1/124

公开(公告)号：US3479457A

公开(公告)日：1969-11-18

申请号：US45404865

申请日：1965-05-07

Applicant: CIT ALCATEL

Inventor： OSWALD JACQUES

IPC: H04L27/18 ,  H04L27/22 ,  H04L27/233 ,  H04L1/00 ,  H04L7/08

CPC classification number: H04L27/2331 ,  H04L27/22 ,  H04L27/2338

公开(公告)号：US3535452A

公开(公告)日：1970-10-20

申请号：US3535452D

申请日：1967-02-16

Applicant: CIT ALCATEL

Inventor： OSWALD JACQUES

IPC: H04L27/18 ,  H04L27/233 ,  H04B1/16

CPC classification number: H04L27/2338

公开(公告)号：FR1404512A

公开(公告)日：1965-07-02

申请号：FR973743

申请日：1964-05-08

Applicant: CIT ALCATEL

Inventor： OSWALD JACQUES

IPC: H04L27/18 ,  H04L27/22 ,  H04L27/233

Abstract: 1,105,447. Data transmission systems; twinplex systems; frequency and phase discriminators. C. I. T. COMPAGNIE INDUSTRIELLE DES TELECOMMUNICATIONS. 4 May, 1965 [8 May, 1964], No. 18825/65. Headings H3A, H4L and H4P. Received frequency or phase-modulated signals are sampled a number of times in the duration of an elementary signal, and the samples are fed to logic circuits which deduce the binary value of the signal by comparison of samples spaced by a given number of samples. Means is provided for eliminating spurious sample values by majority decision technique. In a first embodiment, Fig. 2 (not shown), phase shift signals having differential coding are employed, and there are 12 samples per bit. The samples are fed to a shift register operated at the sampling rate, and the samples in the first and thirteenth cells are passed to an exclusive OR circuit, which gives an output when a phase shift has occurred between those two samples. Thus there is derived for each bit a sequence of ones or zeros, depending on the bit-state. Spurious faults will cause the sequences to be interrupted by zeros or ones, respectively. By feeding the sequences to a majority decision circuit comprising a shift register and gating arrangements, the number of these faults is reduced. Should frequency shift signalling replace that of phase shift it is the first and seventh cells of the register that feed the OR circuit. The system is also described for use where each of four received phase-shifts represents a bit-pair. Chosen cells of the shift register receiving the samples feed three OR circuits and majority decision circuits as in the first embodiment, the resultant signals passing to further shift registers and gates which feed flip-flops, the bit-pairs appearing at the common output of the flip-flops.

公开(公告)号：FR1383789A

公开(公告)日：1965-01-04

申请号：FR946026

申请日：1963-08-29

Applicant: CIT ALCATEL

Inventor： OSWALD JACQUES

IPC: H04L25/49 ,  H03M5/14 ,  H04L27/233

公开(公告)号：DE2129421A1

公开(公告)日：1971-12-23

申请号：DE2129421

申请日：1971-06-14

Applicant: CIT ALCATEL

Inventor： OSWALD JACQUES ,  RAINSARD YVES

IPC: G01S7/35 ,  G06G7/19 ,  H04B7/08 ,  H04B1/10

Abstract: Device for improving the signal/noise ratio of a common signal received on three aerials utilizing correlation between the sum and difference values of combinations of the signals from the three aerials to eliminate or substantially suppress the noise received with the common signal.

公开(公告)号：DE1816760A1

公开(公告)日：1970-04-09

申请号：DE1816760

申请日：1968-12-23

Applicant: CIT ALCATEL

Inventor： OSWALD JACQUES

IPC: H04Q1/457 ,  H03K5/20

Abstract: 1,217,610. Measuring frequencies. COMPAGNIE INDUSTRIELLE DES TELECOMMUNICATIONS. 15 Nov., 1968 [22 Dec., 1967], No. 54464/68. Heading G4H. In a system for identifying two frequencies f1, f2 existing together in a complex waveform, the waveform S(t) is sampled at 3 for polarity, to obtain a first series of pulses (1 or 0), which are applied to a two-stage shift register 6, 7 and the outputs representing successive pairs are compared in a modulo-2 adder 8 which gives a "0" when the inputs are the same and "1" when they are different, the output signals from adder 8 are applied to a 5-stage shift register 9-13, the first two stages 9, 10 being connected to AND gate 14, the first and third, 9 and 11 to AND gate 15 and the "0" outputs from all the stages to AND gate 16, the outputs from the three gates being applied to an OR gate 17. The output signals of OR gate 17 are differentiated at 18 and applied to a bi-stable unit 19, to produce a signal y(t) having a frequency equal to half the difference between the two input frequencies, i.e. ¢(f2 - f1). This signal is applied to a modulo-2 adder 21, receiving signals from sampling device 20 via delay 31, and the adder generates a second train of pulses having a frequency equal to half the sum of the two input frequencies, i.e. ¢(f1 + f2). The sampling pulses are generated at 4 and applied via a frequency doubler 5 to sampler 3 and direct to sampler 20. The sum and difference frequency signals F1 and F2 are converted to a digital representation of the frequency by circuits 22, 23 (Fig. 2, not shown), which are as described in Specification 1,123,641. The actual values of the frequencies f1 and f2 are computed at 24 and indicated on leads 25-30.

公开(公告)号：FR91975E

公开(公告)日：1968-09-06

申请号：FR98324

申请日：1967-03-10

Applicant: CIT ALCATEL

Inventor： OSWALD JACQUES

IPC: H03M1/00 ,  H04L27/156

Abstract: 1,123,641. Digital frequency measuring. COMPAGNIE INDUSTRIELLE DES TELECOMMUNICATIONS. 31 March, 1967 [4 April, 1966; 10 March, 1967], No. 14998/67. Heading G4H. In apparatus for measuring the difference between an unknown frequency and a reference frequency the unknown frequency is sampled for polarity at recurring instants, the samples being translated into binary signals ("1" and "0") and combined in differently spaced pairs in modulo 2 adders, the outputs of which are applied to majority decision circuits to determine whether "1's" or "0's" preponderate, the outputs of the decision circuits then representing in binary code the frequency difference to be measured. If a frequency of F is sampled at the same frequency successive pairs of samples will have the same polarity, i.e. they will both be represented by "1" or by "0". If any pair of pulses is added in a modulus 2 adder the output will be "0". If a frequency F is sampled at half this frequency, alternate samples will have opposite polarity and the adder will give "1". For input frequencies between F and half F some adder outputs will be "1" and some "0", the maj ority indicating that the frequency is nearer F or nearer half F. In the apparatus described, Fig. 2, sampling is effected by a diode gate 2 actuated by clock pulses 3. These pulses are applied as shift pulses to a trigger chain 101-132. The sample pulses from gate 2 are applied to the first stage 101 and the outputs of subsequent stages 102, 104, 108 &c., are applied with the output of gate 2 to half-adders 11, 12, 13 &c. The output of gate 2 and the output of stage 102 represent two samples of a series having a frequency of F. Similarly the output of gate 2 and the output of stage 104 represent two samples of a series having a frequency of half F and so on. Each of the half-adders gives a succession of "1's" or "0's" indicating that the two input samples had different or the same polarity. Majority decision circuits 21, 22, 23 &c., determine which predominate in each adder output, and give a binary signal at 31, 32 &c. These output signals then represent the difference between the input signal and the centre frequency of the band-width of the system. The majority decision circuits (Fig. 3, not shown), each comprise an auxiliary shift register the outputs of which are gated together so that if the majority of signals in the register are "1's" the output will be "1" and if the majority are "0's" the output will be '' 0 ''.

公开(公告)号：DE1512156A1

公开(公告)日：1969-05-14

申请号：DEC0041671

申请日：1967-03-02

Applicant: CIT ALCATEL

Inventor： OSWALD JACQUES

IPC: H04L27/18 ,  H04L27/233 ,  H04B1/16

Abstract: 1,117,724. Data transmission systems. COMPAGNIE INDUSTRIELLE DES TELECOMMUNICATIONS. 28 Feb., 1967 [2 March, 1966], No. 9582/67. Heading H4P. A differentially phase-modulated carrier is demodulated by a logic arrangement in which the carrier is sampled several times in each cycle. The carrier is so modulated that a signal of duration T represents a pair of bits and its phase relative to the preceding period T is (2n + 1) 45 degrees, there being four phases to represent the four possible bit pairs. The carrier frequency is fo = 1/To and period T contains a whole number of half cycles. The received carrier is sampled at intervals of To/8N, N being integral, and each sample is represented as 1 or 0 depending on the instantaneous polarity of the carrier. By use of a shift register fed by the samples binary values x 2 , y 2 , x 1 , y 1 are obtained respectively representing the samples at an arbitrary time t, and at (t-T0/4), (t-T), and (t-T-To/4), Fig. 7 (not shown). These signals pass via respective majority decision circuits to a logic circuit, Figs. 8, 9 (not shown), which derives two bits representing the original bit pair. This is done by four modulo-2 additions, each relating to two of the values x 2 , y 2 , x 1 , Y 1 and their complements, and results in signals m, n p, q, from which, by logical addition and multiplication, signals S 1 (= m + n), S 2 (= p + q), P 1 (= mn), P 2 ( = pq) are derived. The product of each of these signals with its value at a time To/8 earlier is obtained -S 1 1' S 1 2 , P 1 1 , P 1 2 - and the logical additions (S 1 1 + P 1 1 ) and (S 1 2 + P 1 2 ) respectively give the values of the bits of the input bit pair. Further, by modulo-2 addition of the signals P 1 and S 2 at one instant and the values of those signals at a time To/8 earlier, signals P 11 1 and S 11 2 are obtained. Modulo-2 addition of these signals provides a synchronizing signal which has an approximate period T.

公开(公告)号：DE1201862B

公开(公告)日：1965-09-30

申请号：DEC0035811

申请日：1965-05-10

Applicant: CIT ALCATEL

Inventor： BIZET PIERRE ,  OSWALD JACQUES

IPC: H04L27/18 ,  H04L27/20 ,  H04L27/233

Abstract: 1,105,448. Data transmission systems. C.I.T. COMPAGNIE INDUSTRIELLE DES TELECOMMUNICATIONS 7 May, 1965 [12 May, 1964], No. 19483/65 Heading H4P Binary data is transmitted by phase shift, bit-pairs AZ and AA being represented by phase changes of #/2 and #, respectively, and intermediate Z bits by no phase change. The transmitter circuit, described with reference to Fig. 1 (not shown) comprises means to select input bits in a sequence of bit pairs, except that any Z bit which would start such a pair is set aside, the next bit then beginning a new sequence of bit pairs. A gating arrangement fed by the bit pairs, the isolated Z bits, and carrier develops phase shift signals as detailed above: each bit-pair occupies 1¢ carrier cycles. At the receiver. Fig. 3, the signals are sampled twelve times in each bit-pair duration, the samples passing to a 13-cell shift register 23 stepped at sampling rate. The first and thirteenth cells feed an exclusive OR circuit 24, giving an output m. By inversion at 25 m is obtained and, after removal of spurious faulty samples by majority decision at 26 as described in Specification 1,105,447, #m passes to a 3-cell register 28. The outputs #m and #m 1 of the first and third cells pass to gates 29, 30, giving #m#m 1 and #m+#m 1 . These signals trigger flipflops 31, 32 which give pulses of bit-pair and half bit-pair duration which feed an OR gate 33 whose output corresponds to the original binary data.