公开(公告)号：WO2005010926A3

公开(公告)日：2005-09-09

申请号：PCT/FR2004050335

申请日：2004-07-15

Applicant: COMMISSARIAT ENERGIE ATOMIQUE ,  BRUN JEAN ,  PUGET CHRISTIANE

Inventor： BRUN JEAN ,  PUGET CHRISTIANE

IPC: G03F7/00 ,  H01L21/60 ,  H01L21/68

CPC classification number: H01L24/11 ,  H01L21/6835 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/83101 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01061 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/30107

Abstract: The invention relates to a method for production of an anisotropic conductive film which contains a layer of electrically-insulating material and conductive inserts therethrough, said method comprising the following steps: a) forming at least one layer of material, having through-holes, on a substrate, said layer being called the perforated layer , and b) filling said through-holes to form conductive inserts. Said method also comprises producing a mask which at least partially covers a first end of said conductive inserts and etching the unmasked section of the end of said conductive inserts, in order to obtain conductive inserts with tapered ends. Said invention applies to the formation of components (chips, integrated circuits) with high interconnection density.

Abstract translation: 本发明涉及一种用于制造各向异性导电膜的方法，该方法包含一层电绝缘材料和导电插入件，所述方法包括以下步骤：a）至少形成一层具有通孔的材料， 衬底，所述层称为穿孔层，以及b）填充所述通孔以形成导电插入物。 所述方法还包括制造掩模，该掩模至少部分地覆盖所述导电插入件的第一端并蚀刻所述导电插入件的端部的未掩模部分，以便获得具有锥形端部的导电插入件。 所述发明适用于具有高互连密度的部件（芯片，集成电路）的形成。

公开(公告)号：FR2911720A1

公开(公告)日：2008-07-25

申请号：FR0700450

申请日：2007-01-23

Applicant: COMMISSARIAT ENERGIE ATOMIQUE

Inventor： PUGET CHRISTIANE ,  HENRY DAVID

IPC: H01L21/312

Abstract: Une couche polymère (3) est déposée sur une face (5) d'un support (4), ladite face (5) comportant une partie principale plane (5a) et au moins une zone en creux (5b) par rapport à la partie principale plane (5a). La couche polymère (3) est réalisée par au moins les étapes successives suivantes :- dépôt d'une quantité prédéterminée d'un mélange liquide au moins le polymère ou au moins un précurseur dudit polymère sur la partie principale plane (5a) de la face (5) du support (4),- introduction d'au moins une partie du mélange liquide dans la zone en creux (5b) par déplacement d'un cylindre posé sur la partie principale plane (5a) de la face (5)- dépôt d'une quantité supplémentaire de mélange liquide sur la partie principale plane (5a) de la face (5)- et mise en rotation du support (4) selon un axe perpendiculaire au plan de la face (5).

公开(公告)号：FR2857780B1

公开(公告)日：2005-09-09

申请号：FR0350352

申请日：2003-07-18

Applicant: COMMISSARIAT ENERGIE ATOMIQUE

Inventor： BRUN JEAN ,  PUGET CHRISTIANE

IPC: G03F7/00 ,  H01L21/60 ,  H01L21/68 ,  H01L23/492

Abstract: The manufacture of an anisotropic conductor film, called a perforated layer, incorporating a layer of insulating material and some traversing inserts, consists of formation on a substrate with traversing holes; filling the traversing holes to form inserts; the production of a mask covering a first end of the inserts and the engraving of the non-masked part of the end of the inserts to produce pointed ends for the inserts. The manufacture of an anisotropic conductor film, called a perforated layer, incorporating a layer of electrical insulating material and some traversing inserts, consists of: (a) formation on a substrate of at least one layer of material with traversing holes; (b) filling the traversing holes to form the inserts; and (c) production of a mask partially covering a first end of the inserts and the engraving of the non-masked part of the end of the inserts to produce pointed ends for the inserts. Independent claims are also included for the following: (a) the fabrication of a semiconductor chip including the formation of the anisotropic conductor film on a semiconductor slice; and (b) a semiconductor chip fabricated by this method.

公开(公告)号：FR2866753A1

公开(公告)日：2005-08-26

申请号：FR0450349

申请日：2004-02-25

Applicant: COMMISSARIAT ENERGIE ATOMIQUE

Inventor： BRUN JEAN ,  FRANIATTE REMY ,  PUGET CHRISTIANE

IPC: H01L21/60 ,  H01L23/485 ,  H01L23/498 ,  H01L23/482 ,  H01L21/768

Abstract: Fabrication of conducting pins (310) endowed with one or more conductor contacts (302), each coming into contact with an electronic component contact, comprises: (a) deposition of a masking layer on a component; (b) formation of holes in the masking layer; (c) filling these holes with a conducting material to form the conducting pins; (d) removing the masking layer. An independent claim is also included for micro-electronic devices obtained by this method.

公开(公告)号：FR2858111A1

公开(公告)日：2005-01-28

申请号：FR0351044

申请日：2003-12-12

Applicant: COMMISSARIAT ENERGIE ATOMIQUE

Inventor： SOURIAU JEAN CHARLES ,  PUGET CHRISTIANE

IPC: H01L21/56 ,  H01L21/60 ,  H01L21/68 ,  H01L23/31 ,  H01L23/538 ,  H01L25/10 ,  H01L23/28 ,  H01L23/52

Abstract: The method involves forming an interconnections network (3) on a silicon support of a plate (8). An electronic component (4) e.g. chip, is positioned in the network. The electronic component is coated by a coating layer (7) formed above the interconnections network. The plate and the support are separated by removing a sacrificial layer from the support. An independent claim is also included for an electronic compound comprising a stacking of electronic modules.

公开(公告)号：FR2906401A1

公开(公告)日：2008-03-28

申请号：FR0608421

申请日：2006-09-26

Applicant: COMMISSARIAT ENERGIE ATOMIQUE

Inventor： HENRY DAVID ,  PUGET CHRISTIANE

IPC: H01L21/312 ,  B81C1/00

Abstract: Une couche polymère d'une épaisseur prédéterminée est déposée sur une face non plane (3) d'un support (2) selon les étapes successives suivantes :- mise en place du support (2) au-dessus d'un mélange liquide (6) comprenant au moins le polymère ou au moins un précurseur dudit polymère, la face non plane (3) du support (2) étant dirigée vers le bas, en direction du mélange (6),- trempage de la face non plane (3) du support (2) dans ledit mélange (6),- retrait de la face non plane (3) hors dudit mélange (6),- et mise en rotation du support (2) à une vitesse de rotation prédéterminée pour obtenir ladite épaisseur.La couche polymère a, de préférence, une épaisseur uniforme dans le cas d'une face comportant des zones en relief (3b) et, pour une face comportant des zones en creux, les parois des zones en creux ne sont pas recouvertes par la couche polymère.

公开(公告)号：FR2779536A1

公开(公告)日：1999-12-10

申请号：FR9807219

申请日：1998-06-09

Applicant: COMMISSARIAT ENERGIE ATOMIQUE

Inventor： PARAT GUY ,  CAILLAT PATRICE ,  PUGET CHRISTIANE

IPC: G02B6/30 ,  G02B6/36 ,  G02B6/42

Abstract: The invention concerns an assembly for connecting optical fibres with optical or optoelectronic components and a method for making said assembly. The invention is characterised in that it consists in forming at least a fibre support (4, 6) comprising, for each fibre (2), a V-shaped housing; fixing the support and the component (32) to a substrate (12) via fusible links (weld nuggets) (16, 38) and positioning the fibre in the housing so as to obtain a fibre alignment vertical with respect to the component, the horizontal alignment being obtained by means of the melted elements. The invention is applicable in microelectronics.

公开(公告)号：FR2866753B1

公开(公告)日：2006-06-09

申请号：FR0450349

申请日：2004-02-25

Applicant: COMMISSARIAT ENERGIE ATOMIQUE

Inventor： BRUN JEAN ,  FRANIATTE REMY ,  PUGET CHRISTIANE

IPC: H01L23/482 ,  H01L21/60 ,  H01L21/768 ,  H01L23/485 ,  H01L23/498

Abstract: Fabrication of conducting pins (310) endowed with one or more conductor contacts (302), each coming into contact with an electronic component contact, comprises: (a) deposition of a masking layer on a component; (b) formation of holes in the masking layer; (c) filling these holes with a conducting material to form the conducting pins; (d) removing the masking layer. An independent claim is also included for micro-electronic devices obtained by this method.

公开(公告)号：FR2857780A1

公开(公告)日：2005-01-21

申请号：FR0350352

申请日：2003-07-18

Applicant: COMMISSARIAT ENERGIE ATOMIQUE

Inventor： BRUN JEAN ,  PUGET CHRISTIANE

IPC: G03F7/00 ,  H01L21/60 ,  H01L21/68 ,  H01L23/492

Abstract: The manufacture of an anisotropic conductor film, called a perforated layer, incorporating a layer of insulating material and some traversing inserts, consists of formation on a substrate with traversing holes; filling the traversing holes to form inserts; the production of a mask covering a first end of the inserts and the engraving of the non-masked part of the end of the inserts to produce pointed ends for the inserts. The manufacture of an anisotropic conductor film, called a perforated layer, incorporating a layer of electrical insulating material and some traversing inserts, consists of: (a) formation on a substrate of at least one layer of material with traversing holes; (b) filling the traversing holes to form the inserts; and (c) production of a mask partially covering a first end of the inserts and the engraving of the non-masked part of the end of the inserts to produce pointed ends for the inserts. Independent claims are also included for the following: (a) the fabrication of a semiconductor chip including the formation of the anisotropic conductor film on a semiconductor slice; and (b) a semiconductor chip fabricated by this method.

公开(公告)号：FR2779536B1

公开(公告)日：2001-10-19

申请号：FR9807219

申请日：1998-06-09

Applicant: COMMISSARIAT ENERGIE ATOMIQUE

Inventor： PARAT GUY ,  CAILLAT PATRICE ,  PUGET CHRISTIANE

IPC: G02B6/30 ,  G02B6/36 ,  G02B6/42

Abstract: Assembly allowing for connection of optical fibres with optical or optoelectronic components and process for manufacturing this assembly.According to the invention, at least one fibre support (4, 6) is formed including, for each fibre (2), a V-shaped housing. The support and the component (32) are attached to a substrate (12) with meltable elements (16, 38) and the fibre is positioned in the housing so as to vertically align the fibre with the component, horizontal alignment being obtained by the melted elements. Application is to microelectronics.