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    1.
    发明专利
    未知

    公开(公告)号：DE69733101T2

    公开(公告)日：2005-09-29

    申请号：DE69733101

    申请日：1997-06-04

    Applicant: COMPAQ COMPUTER CORP

    Inventor： PETTEY CHRISTOPHER J ,  MACLAREN JOHN M

    IPC: G06F13/36 ,  G06F5/06 ,  G06F13/40

    Abstract: A computer system includes a data storage device on the first data bus, a device on the second data bus, and a bridge device capable of storing multiple data transactions for delivery from the second data bus to the first data bus. The bridge device includes a first data storage buffer preassigned to one of the transactions held in the bridge, and a buffer management element that assigns, if necessary, a second data storage buffer to the data transaction when the data associated with the transaction overflows the first data storage buffer.

    BUS DEVICE DETECTION DEVICE AND METHOD
    3.
    发明专利
    BUS DEVICE DETECTION DEVICE AND METHOD 失效

    公开(公告)号：JPH1055335A

    公开(公告)日：1998-02-24

    申请号：JP16209697

    申请日：1997-06-05

    Applicant: COMPAQ COMPUTER CORP

    Inventor： MACLAREN JOHN M

    IPC: G06F13/36 ,  G06F13/362 ,  G06F13/364

    Abstract: PROBLEM TO BE SOLVED: To decide a treatment against a bus device according to a fact whether the bus device is identical to a multi-threaded device by masking a request signal if a retried bus device is identical to a single threaded device and not masking a request signal if the retried bus device is identical to a multi-threaded device respectively. SOLUTION: The REQ- line of a secondary bus master which produces a retried and delayed read or write request is masked, and the priorities are given to other masters. When a 1st information related to a delayed end signal is returned, the masking of the REQ- line of the corresponding master is immediately canceled and a retried master undergoes again the arbitration. However, in a PCI-PCI bridge 323 serving as a multi-threaded master, an NIC 327B can produce a different request as long as the request that is given to a primary PCI bus 32 from an NIC 327A is retried by a bridge chip 48. Thus, the REQ- line of the multi-threaded master is not masked.

    COMPUTER SYSTEM
    6.
    发明专利
    COMPUTER SYSTEM 失效

    公开(公告)号：JPH11175456A

    公开(公告)日：1999-07-02

    申请号：JP27329898

    申请日：1998-09-28

    Applicant: COMPAQ COMPUTER CORP

    Inventor： MACLAREN JOHN M ,  HAUSAUER BRIAN ,  RAJAGOPALAN USHA

    IPC: G06F13/14 ,  G06F1/00 ,  G06F1/18 ,  G06F3/00 ,  G06F13/40

    Abstract: PROBLEM TO BE SOLVED: To judge adaptability between an extended card and a slot, and to prevent the occurrence of any failure in the card even when they are not adaptable. SOLUTION: When a card is inserted into a slot 98, a decode logic 200 of a PCI bridge 116 receives data related with a signal level and dock frequencies set in the card, and supplies an error signal indicating that the card and the slot are not adaptable, or a signal indicating that a power level is 5 V or 3.3 V to gates 160 and 162 according to the data. When the card and the slot are not adaptable, power switches 170 and 172 are turned off, and a power is not supplied to the slot. When the set power level is 5 V, the power switch 172 is turned on by the gate 160, and when the set power level is 3.3 V, the power switch 172 is turned on by the gate 162, and the power is supplied to the slot. The clock frequencies are judged, and a proper clock is supplied to the card.

    7.
    发明专利
    未知

    公开(公告)号：DE69733101D1

    公开(公告)日：2005-06-02

    申请号：DE69733101

    申请日：1997-06-04

    Applicant: COMPAQ COMPUTER CORP

    Inventor： PETTEY CHRISTOPHER J ,  MACLAREN JOHN M

    IPC: G06F13/36 ,  G06F5/06 ,  G06F13/40

    Abstract: A computer system includes a data storage device on the first data bus, a device on the second data bus, and a bridge device capable of storing multiple data transactions for delivery from the second data bus to the first data bus. The bridge device includes a first data storage buffer preassigned to one of the transactions held in the bridge, and a buffer management element that assigns, if necessary, a second data storage buffer to the data transaction when the data associated with the transaction overflows the first data storage buffer.

    COMPUTER SYSTEM WITH DATA STREAMING CONTROL FUNCTION
    9.
    发明专利
    COMPUTER SYSTEM WITH DATA STREAMING CONTROL FUNCTION 失效

    公开(公告)号：JPH1055336A

    公开(公告)日：1998-02-24

    申请号：JP16210097

    申请日：1997-06-05

    Applicant: COMPAQ COMPUTER CORP

    Inventor： GOODRUM ALAN L ,  MACLAREN JOHN M ,  PETTEY CHRISTOPHER J ,  CULLEY PAUL R

    IPC: G06F13/36 ,  G06F13/362 ,  G06F13/364 ,  G06F13/40

    Abstract: PROBLEM TO BE SOLVED: To improve an overall efficiency of a computer system by starting a supply of data after a requester device acquires again a control right of a 2nd data bus while a data memory device is supplying the requested data to a bridge device. SOLUTION: A delay completion queue(DCQ) 144 stores the delay completion information which is supplied from an upstream chip in response to the delay request transaction that is generated on a secondary bus 32. The DCQ 144 has eight completion buffers, for example, and can hold the completion information on eight line caches at most against a single delay request. In regard to a delay read transaction, the retrieval of the data requested by a requester device is started before a target device stops the supply of data to the DCQ 144 and a data stream is established between a primary bus and the bus 32.

    10.
    发明专利
    未知

    公开(公告)号：DE69732736T2

    公开(公告)日：2005-08-04

    申请号：DE69732736

    申请日：1997-06-04

    Applicant: COMPAQ COMPUTER CORP

    Inventor： MACLAREN JOHN M

    IPC: G06F13/36 ,  G06F13/362 ,  G06F13/364

    Abstract: Access to bus devices on a bus is granted in a computer system, with each bus device asserting a request signal to request the bus. A detector determines if a bus device is multi-threaded or single-threaded. An arbiter masks or does not mask the request signal of a retried bus device based on whether the bus device is a multi-threaded device. The arbiter masks the request signal of a retried bus device if it is a single-threaded device, but does not mask the request signal if the retried bus device is a multi-threaded device. The bus device request includes a delayed request transaction, and the bus includes a PCI bus.

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