公开(公告)号：DE69032655T2

公开(公告)日：1999-02-11

申请号：DE69032655

申请日：1990-10-24

Applicant: COMPAQ COMPUTER CORP

Inventor： MAYER DAVID J ,  CULLEY PAUL R ,  TAYLOR MARK E

IPC: G06F12/02 ,  G06F12/08

Abstract: A computer system has a processor (20) coupled to a cache controller (24), uses page mode memory devices (58) sand performs page hit detection (43) on the processor local bus (26). Column address and data values are latched by a memory controller (62) on memory write operations to allow early completion of the cycle so that the next cycle can partially overlap. This allows the use of economical memories and yet have zero wait state page hit operation.

公开(公告)号：DE69032655D1

公开(公告)日：1998-10-22

申请号：DE69032655

申请日：1990-10-24

Applicant: COMPAQ COMPUTER CORP

Inventor： MAYER DAVID J ,  CULLEY PAUL R ,  TAYLOR MARK E

IPC: G06F12/02 ,  G06F12/08

Abstract: A computer system has a processor (20) coupled to a cache controller (24), uses page mode memory devices (58) sand performs page hit detection (43) on the processor local bus (26). Column address and data values are latched by a memory controller (62) on memory write operations to allow early completion of the cycle so that the next cycle can partially overlap. This allows the use of economical memories and yet have zero wait state page hit operation.