公开(公告)号：DE69434039D1

公开(公告)日：2004-11-04

申请号：DE69434039

申请日：1994-12-30

Applicant: CONS RIC MICROELETTRONICA

Inventor： BRUNO DARIO ,  GIACALONE BIAGIO ,  MANARESI NICOLO ,  GNUDI ANTONIO

IPC: G05F3/24 ,  G05F3/26

Abstract: The transistor threshold extraction circuit in accordance with the present invention has an output (OT) and comprises: a) at least two transistors (M1, M2) of the same type having respectively two control terminals (G1, G2) and having essentially the same threshold with each of said two transistors (M1, M2) also having a first (S1, S2) and a second (D1, D2) main conduction terminal, b) a current mirror (MC) having at least two input-output terminals (IM, OM) with said two terminals (IM, OM) coupled respectively to said two transistors (M1, M2) so as to supply to them the bias currents, c) a voltage generator (VG) connected between said two control terminals (G1, G2), and d) a feedback path (FP) between said control terminals (G1, G2) and one (OM) of said input-output terminals. The output (OT) is coupled to one (G2) of said control terminals.

公开(公告)号：DE69426229T2

公开(公告)日：2001-05-23

申请号：DE69426229

申请日：1994-05-23

Applicant: CONS RIC MICROELETTRONICA

Inventor： GIACALONE BIAGIO ,  CATANIA VINCENZO ,  LUZZI CLAUDIO ,  MATRANGA VINCENZO

IPC: G06F9/44 ,  G06N7/02 ,  G06N7/04 ,  H03K19/20 ,  G06F7/00

Abstract: Method of parallel processing of multiple inference rules (R) organized in fuzzy sets or logical functions of multiple fuzzy sets comprising membership functions (I') defined in a so-called universe of discourse (U) and said inference rules (R) being configured essentially as IF-THEN rules with at least one antecedent preposition and at least one consequent implication and each preposition comprising at least one term (T) of comparison between membership functions (I') and a plurality of input data (I) and each term (T) being separated by logical operators (OL). The method comprises at least one phase of calculation of the weight ( OMEGA ) of each term (T) of the antecedent part of each fuzzy logic inference rule as the greatest value of the intersection between the set of input data (I) and the corresponding membership functions (I').

公开(公告)号：DE69424171T2

公开(公告)日：2001-03-01

申请号：DE69424171

申请日：1994-10-31

Applicant: CONS RIC MICROELETTRONICA

Inventor： BRUNO DARIO ,  GIACALONE BIAGIO ,  MANARESI NICOLO

IPC: G06G7/12 ,  G05F3/24 ,  G06N7/04 ,  G06G7/26

Abstract: Analog processor (2) of antecedent parts of fuzzy logic inference rules and comprising a plurality of analog generators (3) of membership function (FA) each having an output (4) supplying a value corresponding to a degree of truth complemented to one ( alpha ') of logical assignments of the type (A is A') with the outputs (4) being connected together to form a common circuit node (7) and also connected to a current generator (9) and the processor (2) comprising also a voltage control device (5) inserted between a supply voltage pole (VD) and a ground voltage reference (GND) and a one-way element (8) connected to the common circuit node (7) and the one-way element (8) having an output (10) producing an overall degree of truth ( OMEGA ) for the antecedent part of the fuzzy rule to be processed.

公开(公告)号：DE69424171D1

公开(公告)日：2000-05-31

申请号：DE69424171

申请日：1994-10-31

Applicant: CONS RIC MICROELETTRONICA

Inventor： BRUNO DARIO ,  GIACALONE BIAGIO ,  MANARESI NICOLO

IPC: G06G7/12 ,  G05F3/24 ,  G06N7/04 ,  G06G7/26

Abstract: Analog processor (2) of antecedent parts of fuzzy logic inference rules and comprising a plurality of analog generators (3) of membership function (FA) each having an output (4) supplying a value corresponding to a degree of truth complemented to one ( alpha ') of logical assignments of the type (A is A') with the outputs (4) being connected together to form a common circuit node (7) and also connected to a current generator (9) and the processor (2) comprising also a voltage control device (5) inserted between a supply voltage pole (VD) and a ground voltage reference (GND) and a one-way element (8) connected to the common circuit node (7) and the one-way element (8) having an output (10) producing an overall degree of truth ( OMEGA ) for the antecedent part of the fuzzy rule to be processed.

公开(公告)号：DE69432349D1

公开(公告)日：2003-04-30

申请号：DE69432349

申请日：1994-05-23

Applicant: CONS RIC MICROELETTRONICA

Inventor： MATRANGA VINCENZO ,  GIACALONE BIAGIO ,  ABRUZZESE MASSIMO

IPC: G06F9/44 ,  G06N7/02 ,  G06N7/04 ,  H03K19/20

Abstract: Method of parallel processing of multiple inference rules (R) organised in fuzzy sets or logical functions of multiple fuzzy sets comprising membership functions (I') defined in a so-called universe of discourse (U) and said inference rules (R) being configured essentially as IF-THEN rules with at least one antecedent preposition and at least one consequent implication and each preposition comprising at least one term (T) of comparison between membership functions (I') and a plurality of input data (I) and each term (T) being separated by logical operators (OL). The method associates with the logical operators (OL) maximum and minimum operations among two or more elements and calculates exhaustively the overall degree of truth ( OMEGA ) of a rule (R) with a maximum or minimum of N partial truth levels (w).

公开(公告)号：DE69418206D1

公开(公告)日：1999-06-02

申请号：DE69418206

申请日：1994-12-30

Applicant: CONS RIC MICROELETTRONICA

Inventor： BRUNO DARIO ,  GIACALONE BIAGIO ,  MANARESI NICOLO ,  FRANCHI ELEONORA

IPC: G05F3/24 ,  G05F3/26

公开(公告)号：DE69534914D1

公开(公告)日：2006-05-18

申请号：DE69534914

申请日：1995-01-31

Applicant: CONS RIC MICROELETTRONICA

Inventor： GIACALONE BIAGIO ,  BRUNO DARIO ,  MATRANGA VINCENZO ,  MANARESI NICOLO ,  FRANCHI ELEONORA

IPC: G05F3/24 ,  G05F3/26 ,  H03F3/30

Abstract: The present level shift circuit has a first (I1) and a second (I2) input respectively for input of a first and a second voltage signal and an output (OT) and comprises: a) a first transistor (Q1) having a control terminal (G1), a first (S1) and a second (D1) main conduction terminal identifying a main conduction path, and b) a second transistor (Q2) of the same type as said first transistor (Q1) and having a control terminal (G2), a first (S2) and a second (D2) main conduction terminal identifying a main conduction path. The first signal is applied essentially between said control terminal (G1) and said first terminal (S1) of said first transistor (Q1) and said second input (I2) is coupled with the control terminal (G2) of said second transistor (Q2). The currents flowing in the conduction paths of the first (Q1) and the second (Q2) transistors are mutually proportional and one made from the other. The output (OT) is coupled with the first terminal (S2) of the second transistor (Q2). The control terminal (G1) of said first transistor (Q1) is connected to a potential reference (GND). The first signal is applied essentially to said first terminal (S1) of said first transistor (Q1).

公开(公告)号：DE69434039T2

公开(公告)日：2006-02-23

申请号：DE69434039

申请日：1994-12-30

Applicant: CONS RIC MICROELETTRONICA

Inventor： BRUNO DARIO ,  GIACALONE BIAGIO ,  MANARESI NICOLO ,  GNUDI ANTONIO

IPC: G05F3/24 ,  G05F3/26

Abstract: The transistor threshold extraction circuit in accordance with the present invention has an output (OT) and comprises: a) at least two transistors (M1, M2) of the same type having respectively two control terminals (G1, G2) and having essentially the same threshold with each of said two transistors (M1, M2) also having a first (S1, S2) and a second (D1, D2) main conduction terminal, b) a current mirror (MC) having at least two input-output terminals (IM, OM) with said two terminals (IM, OM) coupled respectively to said two transistors (M1, M2) so as to supply to them the bias currents, c) a voltage generator (VG) connected between said two control terminals (G1, G2), and d) a feedback path (FP) between said control terminals (G1, G2) and one (OM) of said input-output terminals. The output (OT) is coupled to one (G2) of said control terminals.

公开(公告)号：DE69531772D1

公开(公告)日：2003-10-23

申请号：DE69531772

申请日：1995-03-30

Applicant: CONS RIC MICROELETTRONICA

Inventor： GIACALONE BIAGIO ,  PAPPALARDO FRANCESCO ,  PELOS ENRICO ,  CATANIA VINCENZO

IPC: G06F9/44 ,  G06N7/02 ,  G06N7/04 ,  G06F7/00

Abstract: A fuzzy processor with improved architecture, comprising a fuzzy rule processor (1), an internal fuzzy instructions memory, and an internal knowledge base memory, characterized in that it comprises an arithmetic-logic unit (2), a control unit (3) adapted to execute non-fuzzy instructions that are typical of conventional microprocessors, and an internal memory (5) comprising the non-fuzzy instructions.

公开(公告)号：DE69426229D1

公开(公告)日：2000-12-07

申请号：DE69426229

申请日：1994-05-23

Applicant: CONS RIC MICROELETTRONICA

Inventor： GIACALONE BIAGIO ,  CATANIA VINCENZO ,  LUZZI CLAUDIO ,  MATRANGA VINCENZO

IPC: G06F9/44 ,  G06N7/02 ,  G06N7/04 ,  H03K19/20 ,  G06F7/00

Abstract: Method of parallel processing of multiple inference rules (R) organized in fuzzy sets or logical functions of multiple fuzzy sets comprising membership functions (I') defined in a so-called universe of discourse (U) and said inference rules (R) being configured essentially as IF-THEN rules with at least one antecedent preposition and at least one consequent implication and each preposition comprising at least one term (T) of comparison between membership functions (I') and a plurality of input data (I) and each term (T) being separated by logical operators (OL). The method comprises at least one phase of calculation of the weight ( OMEGA ) of each term (T) of the antecedent part of each fuzzy logic inference rule as the greatest value of the intersection between the set of input data (I) and the corresponding membership functions (I').