公开(公告)号：JPH07202199A

公开(公告)日：1995-08-04

申请号：JP30758194

申请日：1994-12-12

Applicant: CONS RIC MICROELETTRONICA

Inventor： PIEERO JIORUJIO FUARITSUKA

IPC: H01L27/04 ,  H01L21/822 ,  H01L27/02 ,  H01L27/06 ,  H01L29/78

Abstract: PURPOSE: To prevent a value of clamp voltage from changing, even when a wafer is different by forming a second electrode of a second diode with a second conductivity type first buried region, and forming a first electrode of a second diode with a first conductivity type first doped region. CONSTITUTION: A first diode D1 and a second diode D2, formed in a first conductivity type low doped layer, are provided. The first diode D1 has a first electrode connected to a control electrode of a power semiconductor device and a second electrode connected to a second electrode of the second diode D2, and a first electrode of the second diode D2 is connected to a load drive electrode of the power semiconductor device. Than the second electrode of the second diode D2 is formed with a second conductivity type first buried region 11 buried in the lightly doped layer, and the first electrode of the second diode D2 is formed so as to partially overlap the first buried region 11, with a first conductivity type first doped region 12, extending from the top surface of the semiconductor in the lightly doped layer.