公开(公告)号：JPH07321321A

公开(公告)日：1995-12-08

申请号：JP11716895

申请日：1995-05-16

Applicant: CONS RIC MICROELETTRONICA

Inventor： RAFUAERE ZANBURANO

IPC: H01L27/08 ,  H01L21/336 ,  H01L21/76 ,  H01L27/088 ,  H01L29/78

Abstract: PURPOSE: To prevent the latch-up of the parasitic SCR of a PIC consisting of a vertical-type IGBT and a MOSFET for drive and control. CONSTITUTION: An N -type epitaxial layer 2 is grown on a P -type semiconductor substrate 3 so that an N -type buffer layer 4 is placed between them. A plurality of cells 1 consisting of a deep-P -type layer 40, a shallow N -type layer 6, a poly Si gate 7 being formed on a thin gate oxide film 8 are connected in parallel by a source electrode metal layer 10 according to the amount of power, and an IGBT part where a metal layer 11 is used as a contact electrode is constituted. Also, a MOSFET for drive and control consisting of a source electrode 21, a drain electrode 24, and a gate 20 is formed in a P-type well 15, is surrounded by a deep P -type layer annular region 13 and a P -type-buried region 12, and is completely separated from the IGBT region, thus preventing the latch-up of a parasitic SCR. Also, the same effect can be expected when P-type and the N-type materials are selected inversely.