公开(公告)号：DE69430913D1

公开(公告)日：2002-08-08

申请号：DE69430913

申请日：1994-07-25

Applicant: CONS RIC MICROELETTRONICA

Inventor： BATTAGLIA ANNA ,  FALLICA PIERGIORGIO ,  RONSISVALLE CESARE ,  COFFA SALVATORE ,  RAINERI VITO

IPC: H01L21/22 ,  H01L21/265 ,  H01L21/322 ,  H01L21/331 ,  H01L21/336 ,  H01L21/8222 ,  H01L29/06 ,  H01L29/10 ,  H01L29/167 ,  H01L29/32 ,  H01L29/78 ,  H01L29/16 ,  H01L29/739 ,  H01L27/082

Abstract: A process for the localized reduction of the lifetime of charge carriers, particularly in integrated electronic devices, the particularity whereof is that it comprises the step of implanting ions, at a high dosage and at a high energy level, of a noble gas, advantageously helium, in the active regions of the integrated device so that the ions form bubbles (71a-71d, 72a, 72b) in the active regions (3a, 3b, 2a). A further thermal treatment can be performed after the formation of bubbles of the noble gas in order to improve the structure of the bubbles and to make the noble gas evaporate, so as to leave cavities in the active regions.

公开(公告)号：DE69321965D1

公开(公告)日：1998-12-10

申请号：DE69321965

申请日：1993-12-24

Applicant: CONS RIC MICROELETTRONICA

Inventor： RONSISVALLE CESARE

IPC: H01L21/52 ,  H01L23/051 ,  H01L23/48 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78

公开(公告)号：DE69329999T2

公开(公告)日：2001-09-13

申请号：DE69329999

申请日：1993-12-29

Applicant: CONS RIC MICROELETTRONICA

Inventor： RONSISVALLE CESARE

IPC: H01L21/762 ,  H01L21/822 ,  H01L21/84 ,  H01L27/06 ,  H01L27/12 ,  H01L21/76 ,  H01L21/82

Abstract: A process for the manufacturing of integrated ciruits comprises the steps of: forming an oxide layer (5,6) on at least one surface of two respective semiconductor material wafers (1,2); obtaining a single semiconductor material wafer with a first layer (3,9) and a second layer (2) of semiconductor material and a buried oxide layer (8) interposed therebetween starting from said two semiconductor material wafers (1,2) by direct bonding of the oxide layers (5,6) previously grown; submitting the single wafer to a controlled reduction of the thickness of the first layer (3,9) of semiconductor material; lapping a top surface of the first layer (3,9) of semiconductor material; selectively introducing dopant impurities into selected regions (12,13,14) of the first layer (3,9) of semiconductor material to form the desired integrated components; forming trenches (18) laterally delimiting respective portions of the first layer (3,9) of semiconductor material wherein integrated components are present which are to be electrically isolated from other integrated components; filling the trenches (18) with an insulating material (20).

公开(公告)号：DE69321965T2

公开(公告)日：1999-06-02

申请号：DE69321965

申请日：1993-12-24

Applicant: CONS RIC MICROELETTRONICA

Inventor： RONSISVALLE CESARE

IPC: H01L21/52 ,  H01L23/051 ,  H01L23/48 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78

公开(公告)号：IT1241049B

公开(公告)日：1993-12-29

申请号：IT660690

申请日：1990-03-08

Applicant: CONS RIC MICROELETTRONICA

Inventor： RONSISVALLE CESARE

IPC: H01L29/78 ,  H01L21/331 ,  H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/739 ,  H01L

公开(公告)号：DE69329999D1

公开(公告)日：2001-04-12

申请号：DE69329999

申请日：1993-12-29

Applicant: CONS RIC MICROELETTRONICA

Inventor： RONSISVALLE CESARE

IPC: H01L21/762 ,  H01L21/822 ,  H01L21/84 ,  H01L27/06 ,  H01L27/12 ,  H01L21/76 ,  H01L21/82

Abstract: A process for the manufacturing of integrated ciruits comprises the steps of: forming an oxide layer (5,6) on at least one surface of two respective semiconductor material wafers (1,2); obtaining a single semiconductor material wafer with a first layer (3,9) and a second layer (2) of semiconductor material and a buried oxide layer (8) interposed therebetween starting from said two semiconductor material wafers (1,2) by direct bonding of the oxide layers (5,6) previously grown; submitting the single wafer to a controlled reduction of the thickness of the first layer (3,9) of semiconductor material; lapping a top surface of the first layer (3,9) of semiconductor material; selectively introducing dopant impurities into selected regions (12,13,14) of the first layer (3,9) of semiconductor material to form the desired integrated components; forming trenches (18) laterally delimiting respective portions of the first layer (3,9) of semiconductor material wherein integrated components are present which are to be electrically isolated from other integrated components; filling the trenches (18) with an insulating material (20).

公开(公告)号：IT9006606A1

公开(公告)日：1991-09-09

申请号：IT660690

申请日：1990-03-08

Applicant: CONS RIC MICROELETTRONICA

Inventor： RONSISVALLE CESARE

IPC: H01L29/78 ,  H01L20060101 ,  H01L21/331 ,  H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/739

公开(公告)号：IT9006606D0

公开(公告)日：1990-03-08

申请号：IT660690

申请日：1990-03-08

Applicant: CONS RIC MICROELETTRONICA

Inventor： RONSISVALLE CESARE

IPC: H01L29/78 ,  H01L21/331 ,  H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/739 ,  H01L