公开(公告)号：FR2418989A1

公开(公告)日：1979-09-28

申请号：FR7904222

申请日：1979-02-20

Applicant: CSELT CENTRO STUDI LAB TELECOM

Inventor： CEDOLIN RICCARDO ,  CHIAROTTINO WOLMET ,  GIANDONATO GIUSEPPE ,  GIORCELLI SILVANO ,  MARTINENGO GIORGIO ,  SOFI GIORGIO ,  VILLONE SERGIO

IPC: G06F11/16 ,  G06F15/16 ,  G06F15/177 ,  G06F15/80 ,  H04Q3/545 ,  H04Q3/42 ,  G06F7/00

Abstract: A signal-processing system, e.g. for a telephone exchange, comprises n modular processing units each including a pair of identical microprocessors operating in parallel on binary signals arriving over an internal bus, only one microprocessor of each pair being enabled to transmit outgoing messages to that bus while the other operates as a dummy. The two microprocessors are interlinked by a correlating connection enabling verification of their correct operation in response to microinstructions read out from respective microprogram memories thereof under the control of a common clock. A momentary divergence, resulting from a relative lag in the response of one microprocessor to an asynchronously arriving signal bit, results in a delay of the microprogram by one clock cycle to permit resynchronization; longer-lasting disparities lead to a deactivation of the microprocessor pair and to the emission of an alarm signal. Processing information individual to the associated peripheral unit is stored in an internal memory connected to the bus; general information utilizable by any processing unit is stored in several outside memory banks accessible through external extensions of the internal bus of any such unit. The processing units may be hierarchically organized in several tiers of different ranks.

公开(公告)号：FR2418989B1

公开(公告)日：1987-11-13

申请号：FR7904222

申请日：1979-02-20

Applicant: CSELT CENTRO STUDI LAB TELECOM

Inventor： CEDOLIN RICCARDO ,  CHIAROTTINO WOLMET ,  GIANDONATO GIUSEPPE ,  GIORCELLI SILVANO ,  MARTINENGO GIORGIO ,  SOFI GIORGIO ,  VILLONE SERGIO

IPC: G06F11/16 ,  G06F15/16 ,  G06F15/177 ,  G06F15/80 ,  H04Q3/545 ,  H04Q3/42 ,  G06F7/00

Abstract: A signal-processing system, e.g. for a telephone exchange, comprises n modular processing units each including a pair of identical microprocessors operating in parallel on binary signals arriving over an internal bus, only one microprocessor of each pair being enabled to transmit outgoing messages to that bus while the other operates as a dummy. The two microprocessors are interlinked by a correlating connection enabling verification of their correct operation in response to microinstructions read out from respective microprogram memories thereof under the control of a common clock. A momentary divergence, resulting from a relative lag in the response of one microprocessor to an asynchronously arriving signal bit, results in a delay of the microprogram by one clock cycle to permit resynchronization; longer-lasting disparities lead to a deactivation of the microprocessor pair and to the emission of an alarm signal. Processing information individual to the associated peripheral unit is stored in an internal memory connected to the bus; general information utilizable by any processing unit is stored in several outside memory banks accessible through external extensions of the internal bus of any such unit. The processing units may be hierarchically organized in several tiers of different ranks.

公开(公告)号：IT1111606B

公开(公告)日：1986-01-13

申请号：IT6744778

申请日：1978-03-03

Applicant: CSELT CENTRO STUDI LAB TELECOM

Inventor： CEDOLIN RICCARDO ,  CHIAROTTINO WOLMER ,  GIANDONATO GIUSEPPE ,  GIORCELLI SILVANO ,  MARTINENGO GIORGIO ,  SOFI GIORGIO ,  VILLONE SERGIO

IPC: G06F11/16 ,  G06F15/16 ,  G06F15/177 ,  G06F15/80 ,  H04Q3/545 ,  G06F

Abstract: A signal-processing system, e.g. for a telephone exchange, comprises n modular processing units each including a pair of identical microprocessors operating in parallel on binary signals arriving over an internal bus, only one microprocessor of each pair being enabled to transmit outgoing messages to that bus while the other operates as a dummy. The two microprocessors are interlinked by a correlating connection enabling verification of their correct operation in response to microinstructions read out from respective microprogram memories thereof under the control of a common clock. A momentary divergence, resulting from a relative lag in the response of one microprocessor to an asynchronously arriving signal bit, results in a delay of the microprogram by one clock cycle to permit resynchronization; longer-lasting disparities lead to a deactivation of the microprocessor pair and to the emission of an alarm signal. Processing information individual to the associated peripheral unit is stored in an internal memory connected to the bus; general information utilizable by any processing unit is stored in several outside memory banks accessible through external extensions of the internal bus of any such unit. The processing units may be hierarchically organized in several tiers of different ranks.

公开(公告)号：CA1121513A

公开(公告)日：1982-04-06

申请号：CA322713

申请日：1979-03-02

Applicant: CSELT CENTRO STUDI LAB TELECOM

Inventor： CEDOLIN RICCARDO ,  CHIAROTTINO WOLMER ,  GIANDONATO GIUSEPPE ,  GIORCELLI SILVANO ,  MARTINENGO GIORGIO ,  SOFI GIORGIO ,  VILLONE SERGIO

IPC: G06F11/16 ,  G06F15/16 ,  G06F15/177 ,  G06F15/80 ,  H04Q3/545 ,  G06F11/00

Abstract: In a multiconfigurable modular processing system having an integrated preprocessing system and consisting of a number of specialized modules of different types, each module is optimized so as to be interconnected in processing structures which are differently configurable. One of the modules, which operates as a CPU, is intrinsically duplicated by one identical module, and each of these modules includes means for effecting real time preprocessing of signals as well as normal processing. The system is especially effective as a reliable processing control for the processing of telephone signals.

公开(公告)号：DE2908316A1

公开(公告)日：1979-09-06

申请号：DE2908316

申请日：1979-03-03

Applicant: CSELT CENTRO STUDI LAB TELECOM

Inventor： CEDOLIN RICCARDO ,  CHIAROTTINO WOLMER ,  GIANDONATO GIUSEPPE ,  GIORCELLI SILVANO ,  MARTINENGO GIORGIO ,  SOFI GIORGIO ,  VILLONE SERGIO

IPC: G06F11/16 ,  G06F15/16 ,  G06F15/177 ,  G06F15/80 ,  H04Q3/545 ,  H04Q3/42 ,  G06F7/00 ,  G06F9/00 ,  H03K19/00 ,  H04L11/00

Abstract: A signal-processing system, e.g. for a telephone exchange, comprises n modular processing units each including a pair of identical microprocessors operating in parallel on binary signals arriving over an internal bus, only one microprocessor of each pair being enabled to transmit outgoing messages to that bus while the other operates as a dummy. The two microprocessors are interlinked by a correlating connection enabling verification of their correct operation in response to microinstructions read out from respective microprogram memories thereof under the control of a common clock. A momentary divergence, resulting from a relative lag in the response of one microprocessor to an asynchronously arriving signal bit, results in a delay of the microprogram by one clock cycle to permit resynchronization; longer-lasting disparities lead to a deactivation of the microprocessor pair and to the emission of an alarm signal. Processing information individual to the associated peripheral unit is stored in an internal memory connected to the bus; general information utilizable by any processing unit is stored in several outside memory banks accessible through external extensions of the internal bus of any such unit. The processing units may be hierarchically organized in several tiers of different ranks.