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    SWITCHING ELEMENT FOR SELF-ROUTING MULTISTAGE PACKET- SWITCHING INTERCONNECTION NETWORKS
    2.
    发明专利
    SWITCHING ELEMENT FOR SELF-ROUTING MULTISTAGE PACKET- SWITCHING INTERCONNECTION NETWORKS 未知

    公开(公告)号：CA1280497C

    公开(公告)日：1991-02-19

    申请号：CA551920

    申请日：1987-11-16

    Applicant: CSELT CENTRO STUDI LAB TELECOM

    Inventor： BALBONI GIAN P ,  GIANDONATO GIUSEPPE ,  MELEN RICCARDO ,  VERCELLONE VINICIO

    IPC: H04Q3/42

    Abstract: A switching element for self-routing, multistage, packet-switching, interconnection networks which comprise: an input unit, composed of as many sections ( IMA, IMB) as there are elements inputs, each section comprising a FIFO memory (FIFA, FIFB) for packet buffering; a switch (SW) associated with a control unit (SCU) which, for each packet to be forwarded, sets up a requested connection for that packet between one input and one or more outputs of the element (ECP), based on a routing tag associated with each packet and comprising a first and a second portion relative to normal routing and to broadcasting in the different stages of the network (RC), and solves possible routing conflicts between packets simultaneously arriving at different inputs; and an output unit, composed of as many sections (RUO, RUl) as there are element outputs and performing the functions necessary for correct packet forwarding toward a destination. The control unit (SCU) of the switch (SW) is arranged to handle broadcasting of a packet independently of all other elements (ECP) in the same stage, to allow broadcasting to a number of destinations, not limited to a power of 2, (for an element with two inputs and two outputs) and cooperates with the memory (FIF) storing the packet to be broadcast in such a way that broadcasting does not give rise to internal blocking in the network (RC). The control unit (SCU) moreover solves routing conflicts to set an upper bound to packet residence time within the network.

    4.
    发明专利
    未知

    公开(公告)号：FR2418989A1

    公开(公告)日：1979-09-28

    申请号：FR7904222

    申请日：1979-02-20

    Applicant: CSELT CENTRO STUDI LAB TELECOM

    Inventor： CEDOLIN RICCARDO ,  CHIAROTTINO WOLMET ,  GIANDONATO GIUSEPPE ,  GIORCELLI SILVANO ,  MARTINENGO GIORGIO ,  SOFI GIORGIO ,  VILLONE SERGIO

    IPC: G06F11/16 ,  G06F15/16 ,  G06F15/177 ,  G06F15/80 ,  H04Q3/545 ,  H04Q3/42 ,  G06F7/00

    Abstract: A signal-processing system, e.g. for a telephone exchange, comprises n modular processing units each including a pair of identical microprocessors operating in parallel on binary signals arriving over an internal bus, only one microprocessor of each pair being enabled to transmit outgoing messages to that bus while the other operates as a dummy. The two microprocessors are interlinked by a correlating connection enabling verification of their correct operation in response to microinstructions read out from respective microprogram memories thereof under the control of a common clock. A momentary divergence, resulting from a relative lag in the response of one microprocessor to an asynchronously arriving signal bit, results in a delay of the microprogram by one clock cycle to permit resynchronization; longer-lasting disparities lead to a deactivation of the microprocessor pair and to the emission of an alarm signal. Processing information individual to the associated peripheral unit is stored in an internal memory connected to the bus; general information utilizable by any processing unit is stored in several outside memory banks accessible through external extensions of the internal bus of any such unit. The processing units may be hierarchically organized in several tiers of different ranks.

    6.
    发明专利
    未知

    公开(公告)号：FR2418989B1

    公开(公告)日：1987-11-13

    申请号：FR7904222

    申请日：1979-02-20

    Applicant: CSELT CENTRO STUDI LAB TELECOM

    Inventor： CEDOLIN RICCARDO ,  CHIAROTTINO WOLMET ,  GIANDONATO GIUSEPPE ,  GIORCELLI SILVANO ,  MARTINENGO GIORGIO ,  SOFI GIORGIO ,  VILLONE SERGIO

    IPC: G06F11/16 ,  G06F15/16 ,  G06F15/177 ,  G06F15/80 ,  H04Q3/545 ,  H04Q3/42 ,  G06F7/00

    Abstract: A signal-processing system, e.g. for a telephone exchange, comprises n modular processing units each including a pair of identical microprocessors operating in parallel on binary signals arriving over an internal bus, only one microprocessor of each pair being enabled to transmit outgoing messages to that bus while the other operates as a dummy. The two microprocessors are interlinked by a correlating connection enabling verification of their correct operation in response to microinstructions read out from respective microprogram memories thereof under the control of a common clock. A momentary divergence, resulting from a relative lag in the response of one microprocessor to an asynchronously arriving signal bit, results in a delay of the microprogram by one clock cycle to permit resynchronization; longer-lasting disparities lead to a deactivation of the microprocessor pair and to the emission of an alarm signal. Processing information individual to the associated peripheral unit is stored in an internal memory connected to the bus; general information utilizable by any processing unit is stored in several outside memory banks accessible through external extensions of the internal bus of any such unit. The processing units may be hierarchically organized in several tiers of different ranks.

    8.
    发明专利
    未知

    公开(公告)号：DE2813016A1

    公开(公告)日：1978-10-05

    申请号：DE2813016

    申请日：1978-03-23

    Applicant: CSELT CENTRO STUDI LAB TELECOM

    Inventor： BARCAROLI VALERIO ,  DEMICHELIS CARLO ,  GIANDONATO GIUSEPPE ,  GIORCELLI SILVANO

    IPC: H04Q3/545 ,  H04Q3/54

    Abstract: An apparatus for handling incoming signals from sensors monitoring the state of certain points of a telephone circuit as well as outgoing signals for drivers associated with other circuit points includes a preprocessor PE inserted between the assembly DR of sensors and drivers, on the one hand, and a processor EL, on the other hand. The preprocessor and the processor have access, through a bus 5, to a common memory ME having areas allocated to the scanning of the circuit points, to time-counting operations and to the storage of messages from the preprocessor. A microprogram memory in the preprocessor, when addressed by a sequencer CM started automatically, manually or in response to an instruction from the processor, initiates a temporary seizure of the bus-if the latter is available-whereupon an initial address is delivered from the common memory ME to a working memory ML in the preprocessor to start the scanning of successive pairs of circuit points. If the pair being scanned is connected to sensors, a change of state in either point is reported to the processor if verified by an integration procedure under the control of a read-only memory MIN in the preprocessor; if the points are connected to drivers, the same read-only memory MIN controls the emission of outgoing signals to them. Upon the completion of the scanning operation, the preprocessor performs lower-priority tasks of generating clock messages and measuring signal durations before relinquishing control of the bus.

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