5.
    发明专利
    未知

    公开(公告)号:IT7867782D0

    公开(公告)日:1978-04-10

    申请号:IT6778278

    申请日:1978-04-10

    Abstract: A node in a packet-switching data-transmission network has a processor distributing incoming messages or packets from a receiving buffer to transmitting buffers selected according to routing data established by an updating circuit which algebraically combines incremental delays with respective path delays to obtain total delays assigned to message transmission from the processor over respective transmitting buffers and associated outgoing transmission paths. The increment delays assigned to the respective buffers are calculated by a delay estimator utilizing data from the processor including packet-service times and arrival and departure times of the packets in the various buffers, the path delays assigned to routes extending from the respective transmitting buffers to a terminal node being communicated to the updating circuit via the processor from nodes connected downstream of the transmitting buffers.

    6.
    发明专利
    未知

    公开(公告)号:FR2423109B1

    公开(公告)日:1987-01-16

    申请号:FR7908305

    申请日:1979-04-03

    Abstract: A node in a packet-switching data-transmission network has a processor distributing incoming messages or packets from a receiving buffer to transmitting buffers selected according to routing data established by an updating circuit which algebraically combines incremental delays with respective path delays to obtain total delays assigned to message transmission from the processor over respective transmitting buffers and associated outgoing transmission paths. The increment delays assigned to the respective buffers are calculated by a delay estimator utilizing data from the processor including packet-service times and arrival and departure times of the packets in the various buffers, the path delays assigned to routes extending from the respective transmitting buffers to a terminal node being communicated to the updating circuit via the processor from nodes connected downstream of the transmitting buffers.

    7.
    发明专利
    未知

    公开(公告)号:IT1108325B

    公开(公告)日:1985-12-09

    申请号:IT6778278

    申请日:1978-04-10

    Abstract: A node in a packet-switching data-transmission network has a processor distributing incoming messages or packets from a receiving buffer to transmitting buffers selected according to routing data established by an updating circuit which algebraically combines incremental delays with respective path delays to obtain total delays assigned to message transmission from the processor over respective transmitting buffers and associated outgoing transmission paths. The increment delays assigned to the respective buffers are calculated by a delay estimator utilizing data from the processor including packet-service times and arrival and departure times of the packets in the various buffers, the path delays assigned to routes extending from the respective transmitting buffers to a terminal node being communicated to the updating circuit via the processor from nodes connected downstream of the transmitting buffers.

Patent Agency Ranking