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1.发明专利
公开(公告)号：JP2001053735A
公开(公告)日：2001-02-23
申请号：JP2000188108
申请日：2000-06-22
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： BONELLO ROBERTO , DA DALT NICOLA , MOSCA PAOLO , NERVO GIACOLINO , QUASSO ROBERTO
Abstract: PROBLEM TO BE SOLVED: To obtain a mechanism capable of efficiently and surely operating band width of extremely wide frequency without imposing any synchronization constraint to a data channel to be transmitted. SOLUTION: Input (3) and output (4) are included in a memory (2) for storage of data, the data is inputted as an input data (Pin) stream under control of an input timing signal (XIN) in the input (3) and the data stored in the memory (2) is read as output data (Pout) under control of a reconstruction timing signal (XOUT) from the output (4). The input timing signal (XIN) is used as an input signal and a corresponding output signal (XOUT) with locked phase is generated by a phase locked loop (7). The reconstruction timing signal is obtained from the output signal of the phase locked loop output 7. A means (8) to measure drift transfer of the remaining phase is provided and affects to a transmission functional band of the phase of the phase locked loop output (7) (23, 9, 10). The means is preferable without using any ring filter.
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2.发明专利
公开(公告)号：CA2312114A1
公开(公告)日：2000-12-22
申请号：CA2312114
申请日：2000-06-21
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： MOSCA PAOLO , NERVO GIACOLINO , QUASSO ROBERTO , DA DALT NICOLA , BONELLO ROBERTO
Abstract: A memory (2) for data accumulation includes an input (3) on which such data are entered as a stream of input data (Pin) under the control of an input timing signal (xIN), and an output (4) starting from which the data entered in memory (2) are read as a stream of output data (Pout) under the control of a reconstructed timing signal (XOUT). A phase-locked loop (7) uses this input timing signal (xIN) as an input signal to generate a corresponding phase-locked output signal (xOUT). The reconstructed timing signal is obtained starting from the output signal of such phase-locked loop output (7). Means (8) are provided to measure residual phase wander and act (23, 9, 10) on the transfer function band of the phase of phase-locked loop output (7), which is preferable without ring filters (Figure 1).
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3.发明专利
公开(公告)号：CA2312114C
公开(公告)日：2004-05-04
申请号：CA2312114
申请日：2000-06-21
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： QUASSO ROBERTO , NERVO GIACOLINO , MOSCA PAOLO , DA DALT NICOLA , BONELLO ROBERTO
Abstract: A memory (2) for data accumulation includes an input (3) on which such data are entered as a stream of input data (Pin) under the control of an input timing signal (xIN), and an output (4) starting from which the data entered in memory (2) are rea d as a stream of output data (Pout) under the control of a reconstructed timing signal (XOUT). A phase-locked loop (7) uses this input timing signal (xIN) as an input sign al to generate a corresponding phase-locked output signal (xOUT). The reconstructe d timing signal is obtained starting from the output signal of such phase-locked loop output (7). Means (8) are provided to measure residual phase wander and act (23, 9, 10) on the transfer function band of the phase of phase-locked loop output (7), which i s preferable without ring filters (Figure 1).
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公开(公告)号：IT1308746B1
公开(公告)日：2002-01-10
申请号：ITTO990534
申请日：1999-06-22
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： BONELLO ROBERTO , DA DALT NICOLA , MOSCA PAOLO , NERVO GIACOLINO , QUASSO ROBERTO
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