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公开(公告)号：JP2000353388A
公开(公告)日：2000-12-19
申请号：JP2000145362
申请日：2000-05-17
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： GANDINI MARCO , TORIELLI ALESSANDRO , TUROLLA MAURA
IPC: G11C15/04
Abstract: PROBLEM TO BE SOLVED: To provide a ternary CAM memory(contents address-able memory) which can be designed as an integrated circuit library cell being able to be incorporated in a user device. SOLUTION: In a CAM memory storing data words, bits of the data words can take a neutral logic value other than two complement logic value. The CAM memory includes a matrix(MA) of a memory cell. In this matrix, one pair of cell is allotted to each bit which can take ternary constitution. Access can be enabled so that circuits CT1-CT3, WR, SR; CT11-SR1, CT21-SR2 for controlling the access of a memory matrix performs comparison during CAM mode operation or data is written or read by direct address specifying in RAM mode.
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公开(公告)号：DE69803266T2
公开(公告)日：2002-08-08
申请号：DE69803266
申请日：1998-03-12
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： BELLIFEMINE FABIO , BOLLANO GIANMARIO , GANDINI MARCO , GARINO PIERANGELO , TORIELLI ALESSANDRO , MARCHISIO MAURO , FINOTELLO ANDREA , MOMBERS FREDERICH , DOGIMONT STEPHANIE , GUMM MARTIN , NICOULAZ DIDIER , MATTAVELLI MARCO
IPC: H04N7/32 , G01R31/3185 , H04N7/26 , H04N7/36
Abstract: PCT No. PCT/EP98/01433 Sec. 371 Date Nov. 13, 1998 Sec. 102(e) Date Nov. 13, 1998 PCT Filed Mar. 12, 1998 PCT Pub. No. WO98/42137 PCT Pub. Date Sep. 24, 1998The circuit for motion estimation in digitised video sequence encoders comprises at least an integrated circuit component (IM, IM1 . . . IMn) which is arranged to perform either the function of determining motion vectors and associated costs for different prediction modes, or the function of vector refinement, possibly in addition to prediction mode selection. The circuit (IM) is based on the use of two operating units (M1, M2) which are arranged to concurrently process in different ways different pixel groups according to a MIMD technique. Preferably, when the circuit performs motion vector determination, the operating units (M1, M2) are programmed to execute a genetic algorithm exploiting an initial vector population taking into account the temporal and spatial correlations in the picture.
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公开(公告)号：CA2255900C
公开(公告)日：2002-08-06
申请号：CA2255900
申请日：1998-03-12
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： NICOULAZ DIDIER , GUMM MARTIN , BELLIFEMINE FABIO , DOGIMONT STEPHANIE , MARCHISIO MAURO , FINOTELLO ANDREA , MOMBERS FREDERICH , BOLLANO GIANMARIO , GARINO PIERANGELO , GANDINI MARCO , MATTAVELLI MARCO , TORIELLI ALESSANDRO
IPC: H04N7/32 , G01R31/3185 , H04N7/26 , H04N7/36 , H04N7/50
Abstract: The circuit for motion estimation in digitised video sequence encoders comprises at least an integrated circuit component (IM, IM1...IMn) which is arranged to perform either the function of determining motion vectors and associated costs for different prediction modes, or the function of vector refinement, possibly in addition to prediction mode selection. The circuit (IM) is based on the use of two operating units (M1, M2) which are arranged to concurrently process in different ways different pixel groups according to a MIMD technique. Preferably, when the circuit performs motion vector determination, the operating units (M1, M2) are programmed to execute a genetic algorithm exploiting an initial vector population taking into accoun t the temporal and spatial correlations in the picture.
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公开(公告)号：DE3851003T2
公开(公告)日：1995-03-02
申请号：DE3851003
申请日：1988-05-18
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： LICCIARDI LUIGI , TORIELLI ALESSANDRO
Abstract: The arithmetic-logic unit comprises elementary cells performing logic addition, one per each pair of operand bits, which are particularly optimized as far as carry propagation speed is concerned and are controlled by an auxiliary fast logic allowing their performances to be extended to the other operations; the unit further comprises a control signal generating circuit, subdivided into a first part (DEC1), near the elementary cell of least significant position, which generates an operation selecting signal for all the cells, and into a second part (DEC2), near the elementary cell of most significant position, which generates control signals for the auxiliary logic of each elementary cell.
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公开(公告)号：CA2308969A1
公开(公告)日：2000-11-17
申请号：CA2308969
申请日：2000-05-16
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： TORIELLI ALESSANDRO , TUROLLA MAURA , GANDINI MARCO
Abstract: A content addressable memory. The memory is arranged storing data words whose bits can take on an indifferent logical value besides two complementary logical values. The memory includes a matrix of memory cells in which a pair of cells is assigned to each bit that can take on a ternary configuration. Circuits are provided for memory matrix access control for providing access for performing comparisons during operation in the content addressable memory (CAM) mode or for writing/reading data by means of direct RAM mode addressing.
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Patent Agency Ranking
公开(公告)号：ITTO970209A1
公开(公告)日：1998-09-14
申请号：ITTO970209
申请日：1997-03-14
Applicant: CSELT CENTRO STUDI LAB TELECOM , ECOLE POLYTECH
Inventor： BELLIFEMINE FABIO , BOLLANO GIANMARCO , DOGIMONT STEPHANIE , GANDINI MARCO , GARINO PIERANGELO , GUMM MARTIN , MATTAVELLI MARCO , MOMBERS FREDERICH , NICOULAZ DIDIER , TORIELLI ALESSANDRO
IPC: H04N20060101
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公开(公告)号：DE3851003D1
公开(公告)日：1994-09-15
申请号：DE3851003
申请日：1988-05-18
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： LICCIARDI LUIGI , TORIELLI ALESSANDRO
Abstract: The arithmetic-logic unit comprises elementary cells performing logic addition, one per each pair of operand bits, which are particularly optimized as far as carry propagation speed is concerned and are controlled by an auxiliary fast logic allowing their performances to be extended to the other operations; the unit further comprises a control signal generating circuit, subdivided into a first part (DEC1), near the elementary cell of least significant position, which generates an operation selecting signal for all the cells, and into a second part (DEC2), near the elementary cell of most significant position, which generates control signals for the auxiliary logic of each elementary cell.
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公开(公告)号：CA1282176C
公开(公告)日：1991-03-26
申请号：CA566864
申请日：1988-05-16
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： LICCIARDI LUIGI , TORIELLI ALESSANDRO
Abstract: An integrated circuit implementation of a carry propagating adder and related function incorporates elementary carry-propagating adder cells having two circuit branches, a first of which as an inverter followed by a transfer gate activated when two operands have opposite logic levels, in which case it transfers a complemented carry input to a carry output. The second branch incorporates a 4-transistor series circuit, made up of two P-MOS and two N-MOS transistors, which generates a complemented carry output when the two operands have the same logic level.
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公开(公告)号：IT1308100B1
公开(公告)日：2001-11-29
申请号：ITTO990411
申请日：1999-05-17
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： GANDINI MARCO , TORIELLI ALESSANDRO , TUROLLA MAURA
IPC: G11C15/04
Abstract: A CAM memory is supplied targeted at storing data words whose bits can take on an indifferent logical value besides two complementary logical values. it includes a matrix (MA) of memory cells in which a pair of cells is assigned to each bit that can take on a ternary configuration, circuits (CT1 ... CT3, WR, SR; CT11 ... SR1, CT21 ... SR2) for memory (MA) matrix access control give access for performing comparisons during operation in the CAM mode or for writing/reading data by means of direct RAM mode addressing.
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公开(公告)号：ITTO990411A1
公开(公告)日：2000-11-17
申请号：ITTO990411
申请日：1999-05-17
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： GANDINI MARCO , TUROLLA MAURA , TORIELLI ALESSANDRO
IPC: G11C15/04
Abstract: A CAM memory is supplied targeted at storing data words whose bits can take on an indifferent logical value besides two complementary logical values. it includes a matrix (MA) of memory cells in which a pair of cells is assigned to each bit that can take on a ternary configuration, circuits (CT1 ... CT3, WR, SR; CT11 ... SR1, CT21 ... SR2) for memory (MA) matrix access control give access for performing comparisons during operation in the CAM mode or for writing/reading data by means of direct RAM mode addressing.
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