中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

69 records (took 0.027 seconds)

    IMPROVEMENT OF CONTENTS REFERABLE MEMORY
    1.
    发明专利
    IMPROVEMENT OF CONTENTS REFERABLE MEMORY 失效

    公开(公告)号：JP2000353388A

    公开(公告)日：2000-12-19

    申请号：JP2000145362

    申请日：2000-05-17

    Applicant: CSELT CENTRO STUDI LAB TELECOM

    Inventor： GANDINI MARCO ,  TORIELLI ALESSANDRO ,  TUROLLA MAURA

    IPC: G11C15/04

    Abstract: PROBLEM TO BE SOLVED: To provide a ternary CAM memory(contents address-able memory) which can be designed as an integrated circuit library cell being able to be incorporated in a user device. SOLUTION: In a CAM memory storing data words, bits of the data words can take a neutral logic value other than two complement logic value. The CAM memory includes a matrix(MA) of a memory cell. In this matrix, one pair of cell is allotted to each bit which can take ternary constitution. Access can be enabled so that circuits CT1-CT3, WR, SR; CT11-SR1, CT21-SR2 for controlling the access of a memory matrix performs comparison during CAM mode operation or data is written or read by direct address specifying in RAM mode.

    3.
    发明专利
    未知

    公开(公告)号：DE69803266T2

    公开(公告)日：2002-08-08

    申请号：DE69803266

    申请日：1998-03-12

    Applicant: CSELT CENTRO STUDI LAB TELECOM

    Inventor： BELLIFEMINE FABIO ,  BOLLANO GIANMARIO ,  GANDINI MARCO ,  GARINO PIERANGELO ,  TORIELLI ALESSANDRO ,  MARCHISIO MAURO ,  FINOTELLO ANDREA ,  MOMBERS FREDERICH ,  DOGIMONT STEPHANIE ,  GUMM MARTIN ,  NICOULAZ DIDIER ,  MATTAVELLI MARCO

    IPC: H04N7/32 ,  G01R31/3185 ,  H04N7/26 ,  H04N7/36

    Abstract: PCT No. PCT/EP98/01433 Sec. 371 Date Nov. 13, 1998 Sec. 102(e) Date Nov. 13, 1998 PCT Filed Mar. 12, 1998 PCT Pub. No. WO98/42137 PCT Pub. Date Sep. 24, 1998The circuit for motion estimation in digitised video sequence encoders comprises at least an integrated circuit component (IM, IM1 . . . IMn) which is arranged to perform either the function of determining motion vectors and associated costs for different prediction modes, or the function of vector refinement, possibly in addition to prediction mode selection. The circuit (IM) is based on the use of two operating units (M1, M2) which are arranged to concurrently process in different ways different pixel groups according to a MIMD technique. Preferably, when the circuit performs motion vector determination, the operating units (M1, M2) are programmed to execute a genetic algorithm exploiting an initial vector population taking into account the temporal and spatial correlations in the picture.

    6.
    发明专利
    未知

    公开(公告)号：DE69705139D1

    公开(公告)日：2001-07-19

    申请号：DE69705139

    申请日：1997-02-25

    Applicant: CSELT CENTRO STUDI LAB TELECOM

    Inventor： FINOTELLO ANDREA ,  GANDINI MARCO ,  GARINO PIERANGELO ,  MARCHISIO MAURO

    IPC: H04N7/30 ,  H03M7/30 ,  H03M7/36 ,  H04N7/26 ,  H04N7/32 ,  H04N7/50

    Abstract: An integrated circuit for manipulating digitised video sequences is provided, for use in a system for transmission and reception of compressed video sequences to perform, possibly with the aid of an external memory, re-ordering, format conversion, prediction and motion compensation on the pictures in a sequence. The device (MSM) comprises means (MT1, MT2) for temporarily storing sequences to be manipulated and data read from the external memory; means (DIB) for decoding information about the manipulations to be performed; addressing means (ISS, CM, CME) for transferring the data between the device and the external memory; means (IU, RC) for configuring the device by means of a remote processing unit; means (IHV) for processing the data read from the external memory; means (SU) for arranging the output sequences in the format required by the function to be performed. A controller may control, supervise and set up the functions to be performed.

    7.
    发明专利
    未知

    公开(公告)号：DE792070T1

    公开(公告)日：1998-11-12

    申请号：DE97103018

    申请日：1997-02-25

    Applicant: CSELT CENTRO STUDI LAB TELECOM

    Inventor： FINOTELLO ANDREA ,  GANDINI MARCO ,  GARINO PIERANGELO ,  MARCHISIO MAURO

    IPC: H04N7/30 ,  H03M7/30 ,  H03M7/36 ,  H04N7/26 ,  H04N7/32 ,  H04N7/50

    Abstract: An integrated circuit for manipulating digitised video sequences is provided, for use in a system for transmission and reception of compressed video sequences to perform, possibly with the aid of an external memory, re-ordering, format conversion, prediction and motion compensation on the pictures in a sequence. The device (MSM) comprises means (MT1, MT2) for temporarily storing sequences to be manipulated and data read from the external memory; means (DIB) for decoding information about the manipulations to be performed; addressing means (ISS, CM, CME) for transferring the data between the device and the external memory; means (IU, RC) for configuring the device by means of a remote processing unit; means (IHV) for processing the data read from the external memory; means (SU) for arranging the output sequences in the format required by the function to be performed. A controller may control, supervise and set up the functions to be performed.

    8.
    发明专利
    未知

    公开(公告)号：ITTO960123A1

    公开(公告)日：1997-08-26

    申请号：ITTO960123

    申请日：1996-02-26

    Applicant: CSELT CENTRO STUDI LAB TELECOM

    Inventor： FINOTELLO ANDREA ,  GANDINI MARCO ,  GARINO PIERANGELO ,  MARCHISIO MAURO

    IPC: H04N7/30 ,  H03M7/30 ,  H03M7/36 ,  H04N7/26 ,  H04N7/32 ,  H04N7/50

    Abstract: An integrated circuit for manipulating digitised video sequences is provided, for use in a system for transmission and reception of compressed video sequences to perform, possibly with the aid of an external memory, re-ordering, format conversion, prediction and motion compensation on the pictures in a sequence. The device (MSM) comprises means (MT1, MT2) for temporarily storing sequences to be manipulated and data read from the external memory; means (DIB) for decoding information about the manipulations to be performed; addressing means (ISS, CM, CME) for transferring the data between the device and the external memory; means (IU, RC) for configuring the device by means of a remote processing unit; means (IHV) for processing the data read from the external memory; means (SU) for arranging the output sequences in the format required by the function to be performed. A controller may control, supervise and set up the functions to be performed.

    9.
    发明专利
    未知

    公开(公告)号：NO164947B

    公开(公告)日：1990-08-20

    申请号：NO831320

    申请日：1983-04-14

    Applicant: CSELT CENTRO STUDI LAB TELECOM

    Inventor： GANDINI MARCO ,  TREVISAN DANTE

    IPC: H01L21/82 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H01L27/118 ,  H01L25/03

    Abstract: A basic cell for integrated-circuit gate arrays comprises four transistors (T1, T2, T3, T4), two of which (T2, T3), symmetrical with respect to a cell central point, have the gate electrode (C, C'), connected by a polysilicon pass (1) traversing the metal power lines (Vss, Vdd). A second polysilicon pass (2) connects opposite areas with respect to a zone defined by the metal power lines. The contacts (A, B, C, C', D, D', E, E', G, G', H, H', I, I') associated with the transistor electrodes are arranged so as to minimize the cell surface.

Patent Agency Ranking