公开(公告)号：US09461352B2

公开(公告)日：2016-10-04

申请号：US14253541

申请日：2014-04-15

Applicant: California Institute of Technology

Inventor： Cecile Jung-Kubiak ,  Theodore Reck ,  Goutam Chattopadhyay ,  Jose Vicente Siles Perez ,  Robert H. Lin ,  Imran Mehdi ,  Choonsup Lee ,  Ken B. Cooper ,  Alejandro Peralta

IPC: G02B6/136 ,  H01P3/16 ,  H01P11/00

CPC classification number: H01P3/16 ,  H01P11/002 ,  H01P11/006

Abstract: A multi-step silicon etching process has been developed to fabricate silicon-based terahertz (THz) waveguide components. This technique provides precise dimensional control across multiple etch depths with batch processing capabilities. Nonlinear and passive components such as mixers and multipliers waveguides, hybrids, OMTs and twists have been fabricated and integrated into a small silicon package. This fabrication technique enables a wafer-stacking architecture to provide ultra-compact multi-pixel receiver front-ends in the THz range.

Abstract translation: 已经开发了多步硅蚀刻工艺来制造基于硅的太赫兹（THz）波导部件。 该技术通过批处理功能提供跨多个蚀刻深度的精确尺寸控制。 已经制造了非线性和无源部件，例如混频器和乘法器波导，混合器，OMT和扭曲器并集成到小型硅封装中。 这种制造技术使得晶片堆叠架构能够在太赫兹范围内提供超紧凑的多像素接收机前端。

公开(公告)号：US09791321B2

公开(公告)日：2017-10-17

申请号：US13902529

申请日：2013-05-24

Applicant: California Institute of Technology

Inventor： Goutam Chattopadhyay ,  Ken B. Cooper ,  Emmanuel Decrossas ,  John J. Gill ,  Cecile Jung-Kubiak ,  Choonsup Lee ,  Robert Lin ,  Imran Mehdi ,  Alejandro Peralta ,  Theodore Reck ,  Jose Siles

IPC: G01J5/20 ,  G01S7/02 ,  G01S13/88 ,  G01S13/89 ,  G01J5/00 ,  G01S7/03

CPC classification number: G01J5/20 ,  G01J2005/0077 ,  G01J2005/204 ,  G01S7/02 ,  G01S7/036 ,  G01S13/887 ,  G01S13/89

Abstract: A multi-pixel terahertz transceiver is constructed using a stack of semiconductor layers that communicate using vias defined within the semiconductor layers. By using a stack of semiconductor layers, the various electrical functions of each layer can be tested easily without having to assemble the entire transceiver. In addition, the design allows the production of a transceiver having pixels set 10 mm apart.

公开(公告)号：US10100858B2

公开(公告)日：2018-10-16

申请号：US15337745

申请日：2016-10-28

Applicant: CALIFORNIA INSTITUTE OF TECHNOLOGY

Inventor： Cecile Jung-Kubiak ,  Theodore Reck ,  Bertrand Thomas ,  Robert H. Lin ,  Alejandro Peralta ,  John J. Gill ,  Choonsup Lee ,  Jose V. Siles ,  Risaku Toda ,  Goutam Chattopadhyay ,  Ken B. Cooper ,  Imran Mehdi

IPC: F16B5/02 ,  F16B19/00 ,  H05K13/00

Abstract: A silicon alignment pin is used to align successive layer of component made in semiconductor chips and/or metallic components to make easier the assembly of devices having a layered structure. The pin is made as a compressible structure which can be squeezed to reduce its outer diameter, have one end fit into a corresponding alignment pocket or cavity defined in a layer of material to be assembled into a layered structure, and then allowed to expand to produce an interference fit with the cavity. The other end can then be inserted into a corresponding cavity defined in a surface of a second layer of material that mates with the first layer. The two layers are in registry when the pin is mated to both. Multiple layers can be assembled to create a multilayer structure. Examples of such devices are presented.

公开(公告)号：US09512863B2

公开(公告)日：2016-12-06

申请号：US13871830

申请日：2013-04-26

Applicant: CALIFORNIA INSTITUTE OF TECHNOLOGY

Inventor： Cecile Jung-Kubiak ,  Theodore Reck ,  Bertrand Thomas ,  Robert H. Lin ,  Alejandro Peralta ,  John J. Gill ,  Choonsup Lee ,  Jose V. Siles ,  Risaku Toda ,  Goutam Chattopadhyay ,  Ken B. Cooper ,  Imran Mehdi

IPC: B25G3/00 ,  F16C11/06 ,  F16D1/00 ,  F16G11/00 ,  F16B5/02

CPC classification number: F16B5/025 ,  F16B19/004 ,  H05K13/0015 ,  Y10T29/49778 ,  Y10T29/49895 ,  Y10T403/20

Abstract: A silicon alignment pin is used to align successive layers of components made in semiconductor chips and/or metallic components to make easier the assembly of devices having a layered structure. The pin is made as a compressible structure which can be squeezed to reduce its outer diameter, have one end fit into a corresponding alignment pocket or cavity defined in a layer of material to be assembled into a layered structure, and then allowed to expand to produce an interference fit with the cavity. The other end can then be inserted into a corresponding cavity defined in a surface of a second layer of material that mates with the first layer. The two layers are in registry when the pin is mated to both. Multiple layers can be assembled to create a multilayer structure. Examples of such devices are presented.

Abstract translation: 硅对准销用于对准在半导体芯片和/或金属部件中制造的部件的连续层，以使得具有层状结构的装置的组装更容易。 该销被制成可压缩的结构，其可以被挤压以减小其外径，将一端装配到限定在待组装成层状结构的材料层中的对应的对准袋或空腔中，然后允许膨胀以产生 与空腔的过盈配合。 然后可以将另一端插入限定在与第一层配合的第二材料层的表面中的相应的空腔中。 当引脚与两者配对时，两个层都在注册表中。 可以组装多层以创建多层结构。 呈现这种装置的示例。