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    CONCURRENT FLASHING OF PROCESSING UNITS BY MEANS OF NETWORK RESTRUCTURING
    2.
    发明申请
    CONCURRENT FLASHING OF PROCESSING UNITS BY MEANS OF NETWORK RESTRUCTURING 审中-公开
    用网络重组方式处理单元并发闪烁

    公开(公告)号：WO2006051004A3

    公开(公告)日：2006-12-14

    申请号：PCT/EP2005053446

    申请日：2005-07-18

    Applicant: IBM ,  STAIGER DIETER

    Inventor： STAIGER DIETER

    IPC: G06F15/173

    CPC classification number: G06F15/17375

    Abstract: The present invention provides a network of processing units having at least one switch that allows to disrupt the network between a first and a second processing unit. Disruption of the network by means of the switch effectively disconnects the first processing unit from the network and couples the first processing unit to a controller of the network. The controller is adapted to exchange data with the disconnected processing unit and thereby allows to selectively and directly exchange data with a selected processing unit. In particular in the framework of heterogeneous and hierarchical networks of processing units, the invention provides direct access to processing units and sub-networks and allows for an efficient and fast performance of diagnostic and maintenance procedures of sub-networks and the their corresponding processing units, such as e.g. performing a flashing procedure. By selectively disconnecting a sub-network, flashing can be performed selectively without shutting down of the entire network. Moreover, the invention allows for simultaneous flashing of various sub-networks and for autonomous compensation of network failures by means of the dynamic network restructuring.

    Abstract translation: 本发明提供了一种具有至少一个开关的处理单元网络，该开关允许中断第一和第二处理单元之间的网络。 通过开关破坏网络有效地将第一处理单元从网络断开，并将第一处理单元耦合到网络的控制器。 控制器适合于与断开连接的处理单元交换数据，从而允许选择性地和直接与选择的处理单元交换数据。 特别是在处理单元的异构和分级网络的框架中，本发明提供对处理单元和子网络的直接访问，并且允许子网络及其相应处理单元的诊断和维护过程的高效且快速的执行， 如例如 执行闪烁程序。 通过选择性地断开子网络，闪光可以选择性地执行而不关闭整个网络。 此外，本发明允许通过动态网络重构来同时闪烁各种子网络并自动补偿网络故障。

    METHOD AND CIRCUIT ARRANGEMENT FOR THE GENERATION OF PULSES OF PREDETERMINED TIME RELATION WITHIN PREDETERMINED PULSE INTERVALS WITH HIGH TEMPORAL RESOLUTION
    3.
    发明专利
    METHOD AND CIRCUIT ARRANGEMENT FOR THE GENERATION OF PULSES OF PREDETERMINED TIME RELATION WITHIN PREDETERMINED PULSE INTERVALS WITH HIGH TEMPORAL RESOLUTION 未知

    公开(公告)号：DE3172304D1

    公开(公告)日：1985-10-24

    申请号：DE3172304

    申请日：1981-05-15

    Applicant: IBM DEUTSCHLAND ,  IBM

    Inventor： STAIGER DIETER

    IPC: G01R31/28 ,  G01R31/319 ,  G11C29/00 ,  H03K3/78

    Abstract: In a method for the generation, without dead time, of pulses appearing in successive pulse intervals, with a high time resolution of the pulse intervals and of the pulses, the signals characterizing start (IIN1A, IIN2A) and end (IIN1E, IIN2E) of a pulse interval are generated under storage control by an oscillator (1) for giving coarse time raster values, and a delay circuit (3, 4) series-arranged with the oscillator (1) and with selective (7, 8) delay circuit taps (5, 6) for giving fine time raster values. The signals characterizing the pulse intervals are alternatingly applied to one of two paths (path I, path II), such that the signal characterizing the respective pulse interval start coincides with the coarse time raster predetermined by the oscillator (1). For each path, the leading and trailing edge of a pulse to be generated within a pulse interval is derived via oscillator clock-driven counters (45, 47, 46 and 48) loadable with a count, upon a specific count being reached. Series-arranged to the counters for generating the leading and trailing edges ( 45, 46 and 47, 48) a respective common delay circuit (51 and 52) is provided with storage-controlled (43, 44) selectable delay line taps (62 and 79) for a fine time raster. The pulse information generated on both paths is joined on a common line (65).

    Subsystem board for a computer and computer having such subsystem board
    4.
    发明专利
    Subsystem board for a computer and computer having such subsystem board 未知

    公开(公告)号：GB2459752A

    公开(公告)日：2009-11-11

    申请号：GB0905058

    申请日：2009-03-25

    Applicant: IBM

    Inventor： STAIGER DIETER ,  HUELS HARALD

    IPC: H05K1/02 ,  G11C5/00 ,  H05K1/18

    Abstract: Memory board (210) for a computer system (50), wherein one or more connectors (218) for one or more memory modules (220) are attached to the memory board (210), comprising - a first dedicated board area (222) provided for electrical wiring mainly consisting of signal-integrity-sensitive electrical wiring which electrically connects the one or more connectors (218); and a second dedicated board area (230) provided for memory support electronics (232, 234, 236, 238). The first and second board areas are provided respectively on a first and second board portion. - A third flexible board portion arranged between first and second board portions for connecting these portions. - The first and second board portions are arranged perpendicular to each other.

    5.
    发明专利
    未知

    公开(公告)号：DE2829709A1

    公开(公告)日：1980-01-17

    申请号：DE2829709

    申请日：1978-07-06

    Applicant: IBM DEUTSCHLAND

    Inventor： STAIGER DIETER

    IPC: G01R31/319 ,  G11C29/10 ,  G11C29/56 ,  H03K3/78 ,  H03K3/64 ,  G11C29/00

    Abstract: This discloses a pattern generator having a programmable product cycle timer in which a pulse train, i.e., the pattern generated, having a time raster measurable to one nanosecond can be repeated or switched from a first pulse frequency to a second pulse frequency without the usual transient switching periods between pulses. The invention accomplishes this by providing the generator with a cycle timer using a ten nanosecond clock operating in conjunction with a ten nanosecond down counter so that a pre-selected time interval, before the end of the pulse is achieved, a test is made to determine if a required condition needing a different pulse frequency exists. If such a condition does not exist the present pulse frequency is reinitiated so that at count 0 it is repeated without delay. If the required condition does exist loading of the needed pulse frequency is initiated so that upon termination of the presently existing pulse at count 0, the newly selected pulse will be introduced into the product being tested without delay. A programmable cycle timer is provided to permit the implementation of pulses which has a time raster that is other than a ten nanosecond multiple.

    Integrating consumer electronics devices into an in-car system
    7.
    发明专利
    Integrating consumer electronics devices into an in-car system 未知

    公开(公告)号：GB2460923A

    公开(公告)日：2009-12-23

    申请号：GB0908491

    申请日：2009-05-18

    Applicant: IBM

    Inventor： LAUTENBACH FRANK ,  BUSCH ACHIM ,  LOHMEYER THORSTEN ,  STAIGER DIETER

    IPC: G06F13/10

    Abstract: Additional entities, such as consumer electronic (CE) devices may be integrated into a vehicle electronics system using generic device classes. The vehicle electronics system (10) comprises a human machine interface (HMI), and at least one generic physical and logical interface, A device integrator (20) is connected to the vehicle electronics system (10) via its generic interface and provides connections to additional entities, which may be hot pluggable. The device integrator (20) classifies the connected consumer electronics devices, such as mp3 media players, DVD plaers, gaming consoles, according to their functionality into a set of generic device classes. The integrator translates the individual logical interface protocol of each subsystem group into a generic communication protocol, providing a software or logic driver which is supported by the in car electronics system (10), such that a connected entity may be operated via the HMI without loading any entity specific executable code into said vehicle electronics system. The integration framework may verify the source and integrity so that trusted software is uploaded, to display a specific screen layout for each device class. The integrator may include a USB connection or an FM transmitter for physical adaption to a wireless interface for the vehicle.

    8.
    发明专利
    未知

    公开(公告)号：DE60202857T2

    公开(公告)日：2006-02-09

    申请号：DE60202857

    申请日：2002-02-15

    Applicant: IBM

    Inventor： STAIGER DIETER

    IPC: G10L15/28

    Abstract: In a processor system for audio processing, such as voice recognition and text-to-speech, a dedicated front-end processor, a core processor and a dedicated back-end processor are provided which are coupled by dual access stack. When an analog audio signal is inputted core processor is invoked only when a certain amount of data is present in the dual access stack. Likewise the back-end processor is invoked only when a certain amount of data is present in the dual access stack. This way the overall processing power required by the processing task is minimized as well as the power consumption of the processor system.

    System and method for bi-directional optical transmission of information
    9.
    发明专利
    System and method for bi-directional optical transmission of information 未知

    公开(公告)号：CZ295668B6

    公开(公告)日：2005-09-14

    申请号：CZ312299

    申请日：1997-10-24

    Applicant: IBM

    Inventor： STAIGER DIETER

    IPC: G02B6/43 ,  H04B10/00 ,  H04B10/80

    Abstract: In the present invention, there is described a system for bi-directional optical transmission of information between a plurality of electronic components (3, 5) within a housing by using a diffuse light, the system comprising n different transmission links between each two of the plurality of components (3, 5), and a sheath (12) that prevents mutual interference between the transmission links for at least (n-1) transmission links, the sheath (12) being an integral part of the housing, wherein the n different transmission links are arranged adjacent to one another and the information is transmitted by on-off keying.

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