公开(公告)号：EP0125922A3

公开(公告)日：1987-04-01

申请号：EP84303269

申请日：1984-05-15

Applicant: DATA GENERAL CORPORATION

Inventor： Gershenson, Edward ,  Lemone, Louis A. ,  Lippitt, Mark C.

IPC: G11B05/09 ,  G11B05/012 ,  G06F03/06

CPC classification number: G11B20/1426 ,  G11B5/012 ,  G11B20/12 ,  G11B27/3027 ,  G11B2220/20

Abstract: A SYNC Detected signal (1035) is normally provided by resetting a flip-flop (1237) when a synchronization code in a header or data preamble of a disc sector is detected by logic (1223). Flip-flop (1237) is initially forced set by a signal (1229 or 1231) indicating a header or data preamble should be present. Detection of the code pulls SYNC DET (1225) low to reset the flip-flop (1237) and thereby force SYNC Detected high. If the code is not detected when it should have been, a signal SET SYNC (651) is forced low to reset another flip-flop (1251) which puts SYNCW(12191) low and putsSYNC Detected (1035) high via an inverter (1221). Accordingly data will always be read from a header preamble but the header will not be read correctly and will not match the target header. Data will therefore not be read from or written to the sector.

公开(公告)号：EP0126610A3

公开(公告)日：1986-12-17

申请号：EP84303268

申请日：1984-05-15

Applicant: DATA GENERAL CORPORATION

Inventor： Gershenson, Edward ,  Lemone, Louis A. ,  Faletra, Salvatore ,  Caldara, Stephen ,  Lippitt, Mark C. ,  Braun, William A.

IPC: G06F03/06 ,  G11B05/09

CPC classification number: G06F3/0601 ,  G06F2003/0692

Abstract: The system comprises a controller connected to a disk drive or drives by a bus including data lines and various control and handshaking lines. One line effects a CONTROL/DATA selection so that the drive knows whether codes sent on the data lines are disk data or drive control instructions. Another line effects a HEADER/DATA selection to distinguish the header and data portions of a disk sector. The controller includes a microprocessor (1911) with a register (1969) holding an expected header EHDR, a register (1967) holding the number SCOUNT of sectors to be read or written and a register (1965) holding the number of codes in a sector. in a read or write operation a signal CTLIDDCA from a sequencer (1945) select HEADER and a receiver, selected by a sequencer signal DP/INT, puts received codes on to a data bus (1913). The microprocessor (1911) receives sector headers in this way until there is a match, whereupon a signal CSIGS is given to the sequencer (1945) which causes CTL/DDCA to select DATA and DP/INT to enable the data receiver or driver depending upon whether the operation is read or write. The codes are counted down by decrementing DCOUNT. When DCOUNT = 0 (end of sector) SCOUNT is decremented and another signal CSIGS causes the sequencer to revert to the conditions for looking for the next expected header which is calculated by the microprocessor and entered in EHDR. Where SCOUNT reaches 0 the read or write operation is complete.

公开(公告)号：EP0559454B1

公开(公告)日：1998-05-20

申请号：EP93301620.6

申请日：1993-03-03

Applicant: DATA GENERAL CORPORATION

Inventor： DeYesso, Joseph P. ,  Solomon, Robert C. ,  Todd, Stephen J. ,  Lippitt, Mark C.

IPC: G06F13/40 ,  G06F3/06 ,  G06F11/20

CPC classification number: G06F11/006 ,  G06F11/20 ,  G06F13/4072

Abstract: A method for providing on-line replacement of a module (11) which is at a specified position in an array (10) of modules connected to a common control processor so that all other modules in the array can continue operating during the replacement operation. When the module is removed an indication is provided to the control processor showing that removal has occurred and identifying the position thereof. When the replacement has occurred an indication thereof is provided to the control processor, the replacement module is tested, and the state of the replacement module is updated to place it in the same state it would have been in if it had not been replaced. These indications are given by fingers (40, 42, 45) and pins (41, 43, 44, 46) associated with the backplane connector for the module, which make selective connection as the connector is removed and replaced.

公开(公告)号：EP0125922A2

公开(公告)日：1984-11-21

申请号：EP84303269.9

申请日：1984-05-15

Applicant: DATA GENERAL CORPORATION

Inventor： Gershenson, Edward ,  Lemone, Louis A. ,  Lippitt, Mark C.

IPC: G11B5/09 ,  G11B5/012

CPC classification number: G11B20/1426 ,  G11B5/012 ,  G11B20/12 ,  G11B27/3027 ,  G11B2220/20

Abstract: A SYNC Detected signal (1035) is normally provided by resetting a flip-flop (1237) when a synchronization code in a header or data preamble of a disc sector is detected by logic (1223). Flip-flop (1237) is initially forced set by a signal (1229 or 1231) indicating a header or data preamble should be present. Detection of the code pulls SYNC DET (1225) low to reset the flip-flop (1237) and thereby force SYNC Detected high. If the code is not detected when it should have been, a signal SET SYNC (651) is forced low to reset another flip-flop (1251) which puts SYNCW(12191) low and putsSYNC Detected (1035) high via an inverter (1221). Accordingly data will always be read from a header preamble but the header will not be read correctly and will not match the target header. Data will therefore not be read from or written to the sector.

Abstract translation: 当通过逻辑（1223）检测到扇区的头部或数据前导码中的同步码时，通常通过复位触发器（1237）来提供SYNC检测信号（1035）。 触发器（1237）最初被强制设置为指示报头或数据前同步码应该存在的信号（1229或1231）。 检测到代码将SYNC DET（1225）拉低，以复位触发器（1237），从而强制SYNC检测到高电平。 如果代码未被检测到，则将SET SYNC（651）信号强制为低电平以复位另一个触发器（1251），使SYNCW（1219）为低电平，并通过反相器将SYNC检测到（1035）为高电平 1221）。 因此，数据总是从标题头部读取，但头部将不会被正确读取，并且将不匹配目标头。 因此，数据将不会被读取或写入该行业。

公开(公告)号：EP0559454A1

公开(公告)日：1993-09-08

申请号：EP93301620.6

申请日：1993-03-03

Applicant: DATA GENERAL CORPORATION

Inventor： DeYesso, Joseph P. ,  Solomon, Robert C. ,  Todd, Stephen J. ,  Lippitt, Mark C.

IPC: G06F13/40 ,  G06F3/06 ,  G06F11/20

CPC classification number: G06F11/006 ,  G06F11/20 ,  G06F13/4072

Abstract: A method for providing on-line replacement of a module (11) which is at a specified position in an array (10) of modules connected to a common control processor so that all other modules in the array can continue operating during the replacement operation. When the module is removed an indication is provided to the control processor showing that removal has occurred and identifying the position thereof. When the replacement has occurred an indication thereof is provided to the control processor, the replacement module is tested, and the state of the replacement module is updated to place it in the same state it would have been in if it had not been replaced. These indications are given by fingers (40, 42, 45) and pins (41, 43, 44, 46) associated with the backplane connector for the module, which make selective connection as the connector is removed and replaced.

Abstract translation: 一种用于提供在连接到公共控制处理器的模块的阵列（10）中的指定位置处的模块（11）的在线替换的方法，使得阵列中的所有其他模块可以在替换操作期间继续操作。 当去除模块时，向控制处理器提供指示已经发生移除并且识别其位置的指示。 当发生替换时，将其指示提供给控制处理器，对替换模块进行测试，并更新更换模块的状态，以将其置于与未更换时相同的状态。 这些指示由与模块的背板连接器相关联的手指（40,42,45）和引脚（41,43,44,46）给出，当连接器被移除和更换时，它们进行选择性连接。

公开(公告)号：EP0126610B1

公开(公告)日：1990-08-22

申请号：EP84303268.1

申请日：1984-05-15

Applicant: DATA GENERAL CORPORATION

Inventor： Gershenson, Edward ,  Lemone, Louis A. ,  Faletra, Salvatore ,  Caldara, Stephen ,  Lippitt, Mark C. ,  Braun, William A.

IPC: G06F3/06 ,  G11B5/09

CPC classification number: G06F3/0601 ,  G06F2003/0692

公开(公告)号：EP0126610A2

公开(公告)日：1984-11-28

申请号：EP84303268.1

申请日：1984-05-15

Applicant: DATA GENERAL CORPORATION

Inventor： Gershenson, Edward ,  Lemone, Louis A. ,  Faletra, Salvatore ,  Caldara, Stephen ,  Lippitt, Mark C. ,  Braun, William A.

IPC: G06F3/06 ,  G11B5/09

CPC classification number: G06F3/0601 ,  G06F2003/0692

Abstract: The system comprises a controller connected to a disk drive or drives by a bus including data lines and various control and handshaking lines. One line effects a CONTROL/DATA selection so that the drive knows whether codes sent on the data lines are disk data or drive control instructions. Another line effects a HEADER/DATA selection to distinguish the header and data portions of a disk sector. The controller includes a microprocessor (1911) with a register (1969) holding an expected header EHDR, a register (1967) holding the number SCOUNT of sectors to be read or written and a register (1965) holding the number of codes in a sector. in a read or write operation a signal CTLIDDCA from a sequencer (1945) select HEADER and a receiver, selected by a sequencer signal DP/INT, puts received codes on to a data bus (1913). The microprocessor (1911) receives sector headers in this way until there is a match, whereupon a signal CSIGS is given to the sequencer (1945) which causes CTL/DDCA to select DATA and DP/INT to enable the data receiver or driver depending upon whether the operation is read or write. The codes are counted down by decrementing DCOUNT. When DCOUNT = 0 (end of sector) SCOUNT is decremented and another signal CSIGS causes the sequencer to revert to the conditions for looking for the next expected header which is calculated by the microprocessor and entered in EHDR. Where SCOUNT reaches 0 the read or write operation is complete.

Abstract translation: 该系统包括通过包括数据线和各种控制和握手线的总线连接到磁盘驱动器或驱动器的控制器。 一条线影响CONTROL / DATA选择，以便驱动器知道在数据线上发送的代码是磁盘数据还是驱动器控制指令。 另一行影响HEADER / DATA选择来区分磁盘扇区的头部和数据部分。 控制器包括具有保持预期标题EHDR的寄存器（1969）的微处理器（1911），保存要读或写的扇区数目的数量的寄存器（1967）和保存扇区数目的代码数的寄存器（1965） 。 在读或写操作中，来自定序器（1945）的信号CTL / DDCA选择HEADER和由定序器信号DP / INT选择的接收器将接收到的代码放入数据总线（1913）。 微处理器（1911）以这种方式接收扇区头部直到有一个匹配，由此向定序器（1945）提供信号CSIGS，这导致CTL / DDCA选择DATA和DP / INT以使数据接收器或驱动器依赖于 操作是读还是写。 通过递减DCOUNT来计算代码。 当DCOUNT = 0（扇区结束）时，SCOUNT被递减，另一个信号CSIGS使定序器恢复到寻找由微处理器计算并输入到EHDR中的下一个预期报头的条件。 当SCOUNT达到0时，读取或写入操作完成。

公开(公告)号：EP0125920A2

公开(公告)日：1984-11-21

申请号：EP84303265.7

申请日：1984-05-15

Applicant: DATA GENERAL CORPORATION

Inventor： Gershenson, Edward ,  Lippitt, Mark C.

IPC: G06F3/06 ,  G11B5/09

CPC classification number: G06F3/0601 ,  G06F2003/0692

Abstract: An interface (603) receives data codes and operational instructions on the data lines of a bus (127(1) 127(2)) from a controller and receives control instructions on three control lines of the bus. The control instructions reserve and release the drive initiate sequences in and out and request a status byte from the apparatus. Other control lines select the drive, handshake data transfers, distinguish between data and operational instructions, and send back interrupts. The state of the apparatus is determined by a control unit (609) to which the operational instructions go and which forms a second level of heirarchical control. Flow control instructions (615) from the unit (609) control a data transfer apparatus (605) and read/write processor (611) (third level of heirarchy), the processor including a code converter (133) converting data codes to disk codes and vice versa (fourth level of heirarchy) by means of an encoder/decoder therein (fifth level). The progressively higher levels of the heirarchy operate at progressively higher rates. Data flows set up in the transfer apparatus by the flow control instructions are via a first-in, first-out buffer (607) and comprise operational instructions from interface (603) to control unit (609), data from interface to read// write processor (611) and vice versa for write and read operations. Other flows are possible for diagnostic purposes.

Abstract translation: 接口（603）从控制器接收总线（127（1）127（2））的数据线上的数据代码和操作指令，并在总线的三条控制线上接收控制指令。 控制指令保留并释放驱动器启动序列进出，并从设备请求状态字节。 其他控制线选择驱动器，握手数据传输，区分数据和操作指令，并发回中断。 装置的状态由操作指令所在的控制单元（609）确定，并且形成第二级别的血液控制。 来自单元（609）的流量控制指令（615）控制数据传送装置（605）和读/写处理器（611）（第三级别的混合），处理器包括将数据代码转换为磁盘代码的代码转换器 反之亦然（第四级别），借助于其中的编码器/解码器（第五级）。 越来越多的层级人员以更高的速度运作。 通过流控制指令在传送装置中建立的数据流经由先入先出缓冲器（607）并且包括从接口（603）到控制单元（609）的操作指令，从接口到读/写的数据 处理器（611），反之亦然，用于写入和读取操作。 其他流量可能用于诊断目的。