公开(公告)号：AT405602T

公开(公告)日：2008-09-15

申请号：AT03789983

申请日：2003-11-24

Applicant: DOW GLOBAL TECHNOLOGIES INC ,  IBM

Inventor： HEDRICK JEFFREY ,  SANKARAPANDIAN MUTHUMANICKAM ,  TYBERG CHRISTY ,  GODSCHALX JAMES ,  NIU QING ,  SILVIS H

IPC: C08G61/00 ,  C08G61/10 ,  C08L65/00 ,  C09D165/00 ,  H01L23/532

Abstract: A crosslinked polyarylene material with a reduced coefficient of thermal expansion at high temperatures compared with conventional crosslinked polyarylene materials is provided. In addition, an integrated circuit article containing a crosslinked polyarylene polymer with reduced coefficient of thermal expansion at high temperatures is provided.

公开(公告)号：JP2005051214A

公开(公告)日：2005-02-24

申请号：JP2004187691

申请日：2004-06-25

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： NICHOLSON LEE M ,  TSENG WEI-TSU ,  TYBERG CHRISTY

IPC: H01L21/283 ,  H01L21/304 ,  H01L21/31 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5329 ,  H01L21/76807 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/7684 ,  H01L21/7688 ,  H01L2924/0002 ,  Y10T428/31663 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide an electrical interconnection structure on a substrate including a first low-k dielectric layer, a spin-on low-k CMP protective layer covalently bonded to the first low-k dielectric layer, and a CVD-bonded hard mask/CMP polishing stop layer. SOLUTION: An electrical via 13 and a wire 11 can be formed in a first low-k dielectric layer 3. A spin-on low-k CMP protective layer 5 prevents a damage which may occur on the low-k dielectric 3 due to an uneven CMP process from the center to an edge or in an area varied in metal density. By adjusting the thickness of the low-k CMP protective layer 5, it is possible to respond to a large change in the CMP process without seriously affecting the effective permittivity of a structure 9. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：为了在包括第一低k电介质层，共价键合到第一低k电介质层的旋涂低k CMP保护层的基板上提供电互连结构和CVD 键合硬掩模/ CMP抛光停止层。 解决方案：电通孔13和导线11可以形成在第一低k电介质层3中。自旋低k CMP保护层5防止在低k电介质3上可能发生的损坏 由于从中心到边缘或在金属密度不同的区域中的不均匀CMP工艺。 通过调整低k CMP保护层5的厚度，可以对CMP工艺的大变化作出反应，而不会严重影响结构9的有效介电常数。（C）2005，JPO＆NCIPI

公开(公告)号：JP2004165658A

公开(公告)日：2004-06-10

申请号：JP2003374945

申请日：2003-11-04

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： HEDRICK JEFFREY ,  KANUKU LEE ,  TYBERG CHRISTY ,  FORNOF ANN R

IPC: H01L21/768 ,  H01L21/316 ,  H01L23/522

Abstract: PROBLEM TO BE SOLVED: To provide a combination of an ultralow-dielectric constant dielectric and a dual damascene type Cu interconnecting structure preventing delamination at the time of CMP by enhancing adhesive properties and controlling the resistance of a Cu conductor accurately and uniformly.
SOLUTION: An electrical interconnecting structure 3 on a substrate 1 includes a first porous dielectric layer 5 having a surface region from which a pore forming agent has been removed and an etch stop layer 7 arranged on the first porous dielectric layer. The etch stop layer extends to partially fill the pores in the surface region of the first porous dielectric layer from which the pore forming agent has been removed. Thus, adhesive properties are improved during the subsequent treatment.
COPYRIGHT: (C)2004,JPO