公开(公告)号：EP1857407A2

公开(公告)日：2007-11-21

申请号：EP07075352.0

申请日：2007-05-07

Applicant: Delphi Technologies, Inc.

Inventor： Freeman, John E. ,  Staller, Steven E. ,  Chase, Troy A.

IPC: B81C3/00

CPC classification number: B81C3/002 ,  B81C2201/019

Abstract: A method for fabricating microchip devices is provided. The method includes the steps of providing a first planar substrate (120), locating at least one first alignment feature (128) in the surface (122) of the first planar substrate (120), and bonding a second substrate (140) to the surface (122) of the first planar substrate (120). The method further includes the step of aligning subsequent process operations performed on at least one of the first (120) and second (140) substrates to visible alignment features of the first substrate (120), wherein the visible alignment features are at least one of the first alignment feature (128) and a visible feature that corresponds to the location of the first alignment feature (128).

Abstract translation: 提供了一种用于制造微芯片器件的方法。 该方法包括以下步骤：提供第一平面基板（120），将第一平面基板（120）的表面（122）中的至少一个第一对准特征（128）定位，以及将第二基板（140） 第一平面基板（120）的表面（122）。 该方法还包括将在第一（120）和第二（140）衬底中的至少一个上执行的随后的处理操作与第一衬底（120）的可见对准特征对准的步骤，其中可见对准特征是 第一对准特征（128）和对应于第一对准特征（128）的位置的可见特征。

公开(公告)号：EP1582499A3

公开(公告)日：2006-04-19

申请号：EP05075730.1

申请日：2005-03-29

Applicant: Delphi Technologies, Inc.

Inventor： Chase, Troy A. ,  Logsdon, James H. ,  Kingery, Edward J.

IPC: B81C1/00 ,  B81B7/00 ,  B81C3/00

CPC classification number: B81C1/00333 ,  B81C2203/0118

Abstract: A method of processing a wafer, and particularly a cap wafer (10) configured for mating with a device wafer in the production of a die package (64). Masking layers (20,22) are deposited on oxide layers (16,18) present on opposite surfaces of the wafer (10), after which the masking layers (20,22) are etched to expose regions (32,34,40) of the underlying oxide layers (16,18). Thereafter, an oxide mask (42) is formed on the exposed regions (32,34,40) of the oxide layers (16,18), but is prevented from forming on other regions (44,45,46) of the oxide layers (16,18) masked by the masking layers (20,22). The masking layers (20,22) are then removed and the underlying regions (44,45,46) of the oxide layers (16,18) and the wafer (10) are etched to simultaneously produce through-holes (48) and recesses (50) in the wafer (10). The oxide mask (42) is then removed to allow mating of the cap wafer (10) with a device wafer.

公开(公告)号：EP1582499A2

公开(公告)日：2005-10-05

申请号：EP05075730.1

申请日：2005-03-29

Applicant: Delphi Technologies, Inc.

Inventor： Chase, Troy A. ,  Logsdon, James H. ,  Kingery, Edward J.

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00333 ,  B81C2203/0118

Abstract: A method of processing a wafer, and particularly a cap wafer (10) configured for mating with a device wafer in the production of a die package (64). Masking layers (20,22) are deposited on oxide layers (16,18) present on opposite surfaces of the wafer (10), after which the masking layers (20,22) are etched to expose regions (32,34,40) of the underlying oxide layers (16,18). Thereafter, an oxide mask (42) is formed on the exposed regions (32,34,40) of the oxide layers (16,18), but is prevented from forming on other regions (44,45,46) of the oxide layers (16,18) masked by the masking layers (20,22). The masking layers (20,22) are then removed and the underlying regions (44,45,46) of the oxide layers (16,18) and the wafer (10) are etched to simultaneously produce through-holes (48) and recesses (50) in the wafer (10). The oxide mask (42) is then removed to allow mating of the cap wafer (10) with a device wafer.

Abstract translation: 一种处理晶片的方法，特别是在晶片封装（64）的制造中被配置为与器件晶片配合的盖晶片（10）。 屏蔽层（20,22）沉积在存在于晶片（10）的相对表面上的氧化物层（16,18）上，之后蚀刻掩模层（20,22）以暴露区域（32,34,40） 的下面的氧化物层（16,18）。 此后，氧化物掩模（42）形成在氧化物层（16,18）的暴露区域（32,34,40）上，但是防止在氧化物层（16,18）的其它区域（44,45,46）上形成氧化物掩模 （16,18）被掩蔽层（20,22）掩蔽。 然后去除掩模层（20,22），并且蚀刻氧化物层（16,18）和晶片（10）的下面的区域（44,45,46）以同时产生通孔（48）和凹槽 （50）在晶片（10）中。 然后去除氧化物掩模（42）以允许盖晶片（10）与器件晶片的配合。