公开(公告)号：DE69936277T2

公开(公告)日：2007-10-04

申请号：DE69936277

申请日：1999-04-26

Applicant: ELPIDA MEMORY INC

Inventor： TANIGUCHI JUNYA ,  KOSHIKAWA YASUJI ,  MINE KOUJI

IPC: G01R31/28 ,  G11C29/00 ,  G01R31/317 ,  G11C11/401 ,  G11C11/407 ,  G11C11/413 ,  G11C29/14 ,  G11C29/56

Abstract: According to one disclosed embodiment, a synchronous semiconductor storage device (100) includes a circuit for accomplishing mode setting operations after a test mode is entered, where the test mode includes a higher frequency internal clock. A synchronous semiconductor storage device (100) generates a first internal synchronous clock signal ICLK which can be used to enter mode setting values to a mode register setting circuit (122). At the same time, an external synchronous signal CSB can be applied to generate a second internal synchronous clock signal CSCLK. The ICLK and CSCLK values can be used to generate a higher frequency clock ICLK' in a test mode. The ICLK' signal can be applied to internal circuits (124) allowing such circuits to operate at a higher speed. The ICLK' signal is not applied to the mode register setting circuit (122), thereby avoiding the possible latching of incorrect mode setting values by the mode register setting circuit (122).

公开(公告)号：DE69936277D1

公开(公告)日：2007-07-26

申请号：DE69936277

申请日：1999-04-26

Applicant: ELPIDA MEMORY INC

Inventor： TANIGUCHI JUNYA ,  KOSHIKAWA YASUJI ,  MINE KOUJI

IPC: G01R31/28 ,  G11C29/00 ,  G01R31/317 ,  G11C11/401 ,  G11C11/407 ,  G11C11/413 ,  G11C29/14 ,  G11C29/56

Abstract: According to one disclosed embodiment, a synchronous semiconductor storage device (100) includes a circuit for accomplishing mode setting operations after a test mode is entered, where the test mode includes a higher frequency internal clock. A synchronous semiconductor storage device (100) generates a first internal synchronous clock signal ICLK which can be used to enter mode setting values to a mode register setting circuit (122). At the same time, an external synchronous signal CSB can be applied to generate a second internal synchronous clock signal CSCLK. The ICLK and CSCLK values can be used to generate a higher frequency clock ICLK' in a test mode. The ICLK' signal can be applied to internal circuits (124) allowing such circuits to operate at a higher speed. The ICLK' signal is not applied to the mode register setting circuit (122), thereby avoiding the possible latching of incorrect mode setting values by the mode register setting circuit (122).

公开(公告)号：DE69915158T2

公开(公告)日：2005-04-07

申请号：DE69915158

申请日：1999-04-22

Applicant: ELPIDA MEMORY INC

Inventor： NOBUTOKI TOMOKO ,  MINE KOUJI

IPC: G11C11/41 ,  G11C5/02 ,  G11C5/06 ,  G11C8/10 ,  G11C11/401 ,  H01L27/10 ,  G11C8/00

Abstract: It is an object of the invention to provide a semiconductor memory device with a reduced access time by devising a layout of a circuit without elaborate modification. A Y address buffer is situated on the side of an address pad array (the right side), and outputs a signal for controlling Y address decoder situated on the right side and a circuit block communicated therewith. The Y address decoders on the right side control the Y addresses of memory cells in the memory cell arrays C and D in case that data are read therefrom or written thereinto. The circuit block communicated with the Y address buffer outputs a signal to the address decoders on the side of a DQ pad array (the left side) in accordance with the signal inputted from the Y address buffer. The Y address decoders on the left side control the Y addresses of the memory cells in the memory cell arrays A and B in accordance with the signal inputted from the circuit block communicated with the Y address buffer. Data amplifiers combined with the memory cell arrays A, B, C and d respectively amplify the data read from the memory cells in the memory cell arrays A, B, C and D. The circuit blocks situated on both the side ends of a semiconductor chip respectively output activation signals for activating the data amplifiers combined with the memory cell arrays A, B, C and D. The data amplifier-activation signals outputted from the circuit blocks on the left side end are respectively inputted to the delay circuits DL1 and DL2.