公开(公告)号：DE10061769B4

公开(公告)日：2011-06-01

申请号：DE10061769

申请日：2000-12-12

Applicant: ELPIDA MEMORY INC

Inventor： KITAYAMA MAKOTO ,  OBARA TAKASHI ,  CHONAN TORU ,  FUKUZO YUKIO ,  KOSHIKAWA YASUJI ,  MATSUBARA YASUSHI ,  MITOU HIDEKI

IPC: G11C11/409 ,  G11C11/41 ,  G11C5/02 ,  G11C7/06 ,  G11C7/08 ,  G11C11/401 ,  G11C16/06 ,  H01L21/8242 ,  H01L27/108

公开(公告)号：DE69936277D1

公开(公告)日：2007-07-26

申请号：DE69936277

申请日：1999-04-26

Applicant: ELPIDA MEMORY INC

Inventor： TANIGUCHI JUNYA ,  KOSHIKAWA YASUJI ,  MINE KOUJI

IPC: G01R31/28 ,  G11C29/00 ,  G01R31/317 ,  G11C11/401 ,  G11C11/407 ,  G11C11/413 ,  G11C29/14 ,  G11C29/56

Abstract: According to one disclosed embodiment, a synchronous semiconductor storage device (100) includes a circuit for accomplishing mode setting operations after a test mode is entered, where the test mode includes a higher frequency internal clock. A synchronous semiconductor storage device (100) generates a first internal synchronous clock signal ICLK which can be used to enter mode setting values to a mode register setting circuit (122). At the same time, an external synchronous signal CSB can be applied to generate a second internal synchronous clock signal CSCLK. The ICLK and CSCLK values can be used to generate a higher frequency clock ICLK' in a test mode. The ICLK' signal can be applied to internal circuits (124) allowing such circuits to operate at a higher speed. The ICLK' signal is not applied to the mode register setting circuit (122), thereby avoiding the possible latching of incorrect mode setting values by the mode register setting circuit (122).

公开(公告)号：DE102004048652A1

公开(公告)日：2005-06-30

申请号：DE102004048652

申请日：2004-10-06

Applicant: ELPIDA MEMORY INC

Inventor： KOSHIKAWA YASUJI

IPC: G11C29/04 ,  G11C11/406 ,  G11C29/00

Abstract: At first, failed cells are repaired using row redundancy or column redundancy as done in the past and then, for the remaining failed cells that cannot be repaired by row or column redundancy, by increasing the number of refreshes greater than that of normal cells, it is possible to repair more failed cells.

公开(公告)号：DE69936277T2

公开(公告)日：2007-10-04

申请号：DE69936277

申请日：1999-04-26

Applicant: ELPIDA MEMORY INC

Inventor： TANIGUCHI JUNYA ,  KOSHIKAWA YASUJI ,  MINE KOUJI

IPC: G01R31/28 ,  G11C29/00 ,  G01R31/317 ,  G11C11/401 ,  G11C11/407 ,  G11C11/413 ,  G11C29/14 ,  G11C29/56

Abstract: According to one disclosed embodiment, a synchronous semiconductor storage device (100) includes a circuit for accomplishing mode setting operations after a test mode is entered, where the test mode includes a higher frequency internal clock. A synchronous semiconductor storage device (100) generates a first internal synchronous clock signal ICLK which can be used to enter mode setting values to a mode register setting circuit (122). At the same time, an external synchronous signal CSB can be applied to generate a second internal synchronous clock signal CSCLK. The ICLK and CSCLK values can be used to generate a higher frequency clock ICLK' in a test mode. The ICLK' signal can be applied to internal circuits (124) allowing such circuits to operate at a higher speed. The ICLK' signal is not applied to the mode register setting circuit (122), thereby avoiding the possible latching of incorrect mode setting values by the mode register setting circuit (122).

公开(公告)号：DE102004055216A1

公开(公告)日：2005-07-07

申请号：DE102004055216

申请日：2004-11-16

Applicant: ELPIDA MEMORY INC

Inventor： KOSHIKAWA YASUJI ,  DONO CHIAKI

IPC: G11C11/409 ,  G11C7/12 ,  G11C11/407 ,  G11C11/4094

Abstract: A semiconductor storage device in which the chip area is prevented from increasing to reduce the leakage current during low power (power down) time caused by shorting across bit and word lines due to crossing failure. There are provided precharge equalizing NMOS transistors the gates of which are supplied with a control signal (BLEQT). These precharge equalizing NMOS transistors are connected across a power supply line (VNLR), supplying a precharge potential to the bit line, and the bit line. At the time of low power operation, a potential (0.7 to 1.4V) lower than the potential VPP (e.g. 3.2V) applied during the precharge operation of the normal operation is supplied to the gate terminals of the transistors to reduce the leakage current caused by shorting across the bit and word lines caused in turn by crossing failure.