公开(公告)号：DE69829039D1

公开(公告)日：2005-03-24

申请号：DE69829039

申请日：1998-12-30

Applicant: ELPIDA MEMORY INC

Inventor： MOCHIDA YOSHIFUMI

IPC: G11C11/407 ,  G11C7/10 ,  G11C7/00

Abstract: A semiconductor storage device (100) having a burst mode capability for accomplishing a rapid pipeline operation is disclosed. A signal delay device (104), such as a first-in-first-out buffer (FIFO), is disposed between the data read circuitry of a memory cell array (102) and an output buffer (106). The signal delay device (104) is composed of a plurality of storage circuits (206-0 and 206-1) connected in parallel. Data values are input to selected of the storage circuits (206-0 and 206-1) by input control signals (DSEL0-DSEL1) and output from selected of the storage circuits (206-0 and 206-1) by output control signals (OSEL0-OSEL1). The DSEL0-DSEL1 and OSEL0-OSEL1 signals are generated in response to count signals (OCNT0-OCNT1).

公开(公告)号：DE69829039T2

公开(公告)日：2006-02-09

申请号：DE69829039

申请日：1998-12-30

Applicant: ELPIDA MEMORY INC

Inventor： MOCHIDA YOSHIFUMI

IPC: G11C11/407 ,  G11C7/00 ,  G11C7/10

Abstract: A semiconductor storage device (100) having a burst mode capability for accomplishing a rapid pipeline operation is disclosed. A signal delay device (104), such as a first-in-first-out buffer (FIFO), is disposed between the data read circuitry of a memory cell array (102) and an output buffer (106). The signal delay device (104) is composed of a plurality of storage circuits (206-0 and 206-1) connected in parallel. Data values are input to selected of the storage circuits (206-0 and 206-1) by input control signals (DSEL0-DSEL1) and output from selected of the storage circuits (206-0 and 206-1) by output control signals (OSEL0-OSEL1). The DSEL0-DSEL1 and OSEL0-OSEL1 signals are generated in response to count signals (OCNT0-OCNT1).

公开(公告)号：DE10135065B4

公开(公告)日：2010-01-28

申请号：DE10135065

申请日：2001-07-18

Applicant: ELPIDA MEMORY INC

Inventor： MOCHIDA YOSHIFUMI

IPC: G11C8/08 ,  G11C11/407 ,  G11C7/02 ,  G11C8/10 ,  G11C8/14 ,  G11C11/401 ,  G11C11/408

Abstract: A semiconductor memory device (10) having a peripheral ground line (GND) receiving charge when discharging a sub-word line (SWL) is provided. The semiconductor memory device (10) can include a row decoder (XDEC1), RA driver (RAD11), and sub-decoder blocks (SB). Row decoder (XDEC1) may activate a main word line (MWL) based on a received address value. RA driver (RAD11) may activate a sub-decoder block (SB) from a group of sub-decoder blocks coupled to the activated main word line (MWL). RA driver (RAD11) may provide a current path (4) to peripheral ground (GND) when the sub-word line (SWL) transitions from the activated state to the unactivated state. Non-selected sub-word lines may have a current path (1, 2, or 3) to a word line ground (GNDXDEC) for holding the other word lines at a "quiet" ground potential. Noise produced from discharging a sub-word line may not affect non-selected word lines.

公开(公告)号：JP2013097844A

公开(公告)日：2013-05-20

申请号：JP2011241619

申请日：2011-11-02

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： OKUMOTO SHINJI ,  MOCHIDA YOSHIFUMI

IPC: G11C29/14

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device that autonomously resets a test mode instead of resetting the test mode dependently on the common standard of the semiconductor.SOLUTION: A semiconductor device comprises: a first test unit that enables a test of an internal circuit; a second test unit that can control the operation state of the first test unit; and a test reset unit that is activated in response to releasing the reset state of the first test unit and generates a reset signal after a predetermined period has passed since the activation of the first test unit. The second test unit sets the first test unit to a reset state when receiving the reset signal generated by the test reset unit.

Abstract translation: 要解决的问题：提供一种自主地重置测试模式的半导体器件，而不是依赖于半导体的共同标准来重置测试模式。 解决方案：半导体器件包括：第一测试单元，其能够进行内部电路的测试; 第二测试单元，其可以控制第一测试单元的操作状态; 以及测试复位单元，其响应于释放所述第一测试单元的复位状态而被激活，并且在从所述第一测试单元的激活经过预定时段之后产生复位信号。 第二测试单元在接收到由测试复位单元生成的复位信号时将第一测试单元设置为复位状态。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：JP2011252802A

公开(公告)日：2011-12-15

申请号：JP2010126945

申请日：2010-06-02

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： OKUMOTO MASASHI ,  MOCHIDA YOSHIFUMI

IPC: G01R31/28 ,  H01L21/822 ,  H01L27/04

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device for initializing using a test mode the output of a level adjustment circuit erroneously set up when the power supply is turned on, and adjusting the output of the level adjustment circuit at a high speed to a regular setting value that is a target level.SOLUTION: The semiconductor device comprises: a plurality of latch circuits 2 for holding test data inputted from the outside in a test mode; a decode circuit 3 for inputting the test data held by the latch circuits 2 to generate a code by a combination of logic of the test data; a transition detection circuit 7 for outputting gate drive signals UPDN_B , UPDN_T , and UPDN_T which are at an H level or an L level during a preset period when the logic level of the test data held by the latch circuits 2 changes to drive a current supply circuit (a reducing circuit 8, a raising circuit 9).

Abstract translation: 要解决的问题：为了提供使用测试模式初始化的半导体器件，当电源接通时错误地设置的电平调节电路的输出，并且调整 以高速作为目标水平的常规设定值。 解决方案：半导体器件包括：多个锁存电路2，用于在测试模式下保持从外部输入的测试数据; 解码电路3，用于输入由锁存电路2保持的测试数据，以通过测试数据的逻辑的组合生成代码; 一个转换检测电路7，用于在预设时段期间输出作为H电平或L电平的门电路驱动信号UPDN_B，UPDN_T，和UPDN_T

公开(公告)号：JP2008153253A

公开(公告)日：2008-07-03

申请号：JP2006336590

申请日：2006-12-14

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： MOCHIDA YOSHIFUMI

IPC: H01L21/822 ,  H01L21/82 ,  H01L27/04 ,  H03K5/1252

CPC classification number: G11C29/46

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device in which malfunction in a signal-using circuit can be prevented without increasing the man-hour of layout. SOLUTION: A test mode decode & latch circuit 101 decodes an input signal based on a latch signal TMRS to generate a TEST1 signal. A TEST1 signal line 103 has a high resistance interconnect portion 103a and a low resistance interconnect portion 103b. A latch circuit 105 for latching the TEST1 signal outputted from the test mode decode & latch circuit 101 based on the latch signal TMRS is inserted into the low resistance interconnect portion. The latch circuit 105 brings a switching buffer 151 into inactive state at such a timing as the TEST1 signal does not change. Consequently, even if the potentials at the high resistance interconnect portion 103a and the low resistance interconnect portion 103b vary due to impact of transition noise from an adjacent interconnection, that variation has no effect on the output from the latch circuit 105. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种其中可以防止信号使用电路中的故障而不增加布局的工时的半导体器件。 解决方案：测试模式解码和锁存电路101基于锁存信号TMRS对输入信号进行解码，以生成TEST1信号。 TEST1信号线103具有高电阻互连部分103a和低电阻互连部分103b。 基于锁存信号TMRS将从测试模式解码和锁存电路101输出的TEST1信号锁存的锁存电路105被插入到低电阻互连部分中。 在TEST1信号不改变的定时，锁存电路105使切换缓冲器151进入非活动状态。 因此，即使高电阻互连部分103a和低电阻互连部分103b上的电位由于来自相邻互连线的过渡噪声的影响而变化，该变化对锁存电路105的输出没有影响。 （C）2008，JPO＆INPIT

公开(公告)号：JP2013171608A

公开(公告)日：2013-09-02

申请号：JP2012036418

申请日：2012-02-22

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： JINNO TOMOYUKI ,  MOCHIDA YOSHIFUMI

IPC: G11C29/00 ,  G11C11/401

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device in which information on defective memory elements in a redundancy area can be used in later test processes, so as to prevent an increase in screening costs which is caused when a test for the redundancy area is required in the later test processes because information indicating that there is a defective redundant memory element cannot be stored when the defective redundant memory element is found to exist in the redundancy area.SOLUTION: A semiconductor device comprises: memory elements that store data; a defective memory element that is one of the memory elements and determined to be defective; a redundant memory element with which replacement can be done; and a first nonvolatile storage element that stores, when the redundant memory element is determined to be defective, information on the address of the defective redundant memory element.

Abstract translation: 要解决的问题：提供一种半导体器件，其中可以在后面的测试过程中使用冗余区域中的缺陷存储器元件的信息，以便防止在需要冗余区域的测试时引起的筛选成本的增加 在后续的测试过程中，因为当发现有缺陷的冗余存储器元件存在于冗余区域中时，不能存储指示存在有缺陷的冗余存储元件的信息。解决方案：半导体器件包括：存储数据的存储器元件; 作为存储元件之一并被确定为有缺陷的缺陷存储元件; 冗余存储器元件，可以进行更换; 以及第一非易失性存储元件，其在冗余存储元件被确定为有缺陷时存储关于有缺陷的冗余存储元件的地址的信息。

公开(公告)号：JP2011134386A

公开(公告)日：2011-07-07

申请号：JP2009292959

申请日：2009-12-24

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： TAJIMA SHINGO ,  MOCHIDA YOSHIFUMI

IPC: G11C29/34

CPC classification number: G11C29/02 ,  G11C29/024 ,  G11C29/025 ,  G11C2029/1204

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device capable of detecting defects of a column selection line. SOLUTION: A semiconductor device includes: a comparison circuit 111 that compares a plurality of pieces of read data B10 to B13 which are simultaneously read through data wirings DL10 to DL13 with expected values A0 to A3 and generates comparison results C10 to C13; an AND gate 120 that activates a determination signal S1 in response to a fact that at least one of the comparison results C10 to C13 shows a disagreement; and an OR gate 130 that activates a determination signal S2 in response to a fact that all of the comparison results C10 to C13 show disagreements. With this arrangement, when a test for detecting a bad address is performed in a wafer state, a defect of a column selection line can be detected. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供能够检测列选择线的缺陷的半导体器件。 解决方案：半导体器件包括：比较电路111，其将通过数据布线DL10至DL13同时读取的多条读取数据B10至B13与期望值A0至A3进行比较，并生成比较结果C10至C13; 与门120，其响应于比较结果C10至C13中的至少一个显示不一致的事实来激活确定信号S1; 以及OR门130，其响应于所有比较结果C10至C13显示不同的事实来激活确定信号S2。 通过这种布置，当在晶片状态下执行用于检测错误地址的测试时，可以检测列选择线的缺陷。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2011096337A

公开(公告)日：2011-05-12

申请号：JP2009251776

申请日：2009-11-02

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： OKUMOTO SHINJI ,  MOCHIDA YOSHIFUMI

IPC: G11C29/06

Abstract: PROBLEM TO BE SOLVED: To reduce an increase in current consumption during a stress test.
SOLUTION: A semiconductor memory device includes: a local IO line LIO and a main IO line MIO to be used for input and output of data to and from a memory cell, with one end connected to each other; a circuit block VBLPBF which applies a voltage having a VDL level to the other end of the local IO line LIO in a first test mode; and a circuit block WAMP which applies a voltage having a VDD level to the other end of the main IO line MIO in a second test mode. The semiconductor memory device includes a circuit block BLEQCT which outputs a control signal BLEQ' having different voltage levels depending on the first and second test modes, and a transfer gate which limits the value of a current flowing through the local IO line LIO and the main IO line MIO, in the first and second test mode, based on the control signal BLEQ'.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：减少压力测试期间电流消耗的增加。 解决方案：一种半导体存储器件包括：本地IO线LIO和主IO线MIO，用于将数据输入和输出到存储器单元，其一端彼此连接; 电路块VBLPBF，其在第一测试模式中将具有VDL电平的电压施加到本地IO线LIO的另一端; 以及在第二测试模式中将具有VDD电平的电压施加到主IO线MIO的另一端的电路块WAMP。 该半导体存储器件包括电路块BLEQCT，该电路块BLEQCT根据第一和第二测试模式输出具有不同电压电平的控制信号BLEQ'，以及限制流经本地IO线LIO和主器件的电流的值的传输门 IO线MIO在第一和第二测试模式下，基于控制信号BLEQ'。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2008165854A

公开(公告)日：2008-07-17

申请号：JP2006351296

申请日：2006-12-27

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： MOCHIDA YOSHIFUMI

IPC: G11C11/403 ,  G11C11/406

CPC classification number: G11C11/406 ,  G11C11/40611 ,  G11C11/40615

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor memory which can activate the cell array according to the refresh mode without increasing the number of wirings and circuit area. SOLUTION: The circuit of the oscillator 102 is constituted so that its oscillation cycle can be adjusted by the CODEi output from the ROM circuit 103 and the cycle is set to p times a tRAS period in self refreshing. The n bit counter 106 counts up based on the output of the oscillator 102. The programmable decoder 107 issues a reset signal to the n bit counter at a cycle q times the oscillator cycle based on the count of the n bit counter 106 and the CODEj the ROM circuit 104 outputs. Each time the programmable decoder 107 outputs a reset signal, this memory controls the SRACT at an H level for the period 1/p times the OSC0 cycle to activate the RASB signal. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种可以根据刷新模式激活单元阵列的半导体存储器，而不增加布线数量和电路面积。 解决方案：振荡器102的电路被构造成使得其振荡周期可以通过来自ROM电路103的CODEi输出进行调整，并且在自刷新中将周期设置为p倍于tRAS周期。 n位计数器106基于振荡器102的输出进行计数。可编程解码器107基于n位计数器106和CODEj的计数以振荡器周期q倍的周期向n位计数器发出复位信号 ROM电路104输出。 每当可编程解码器107输出复位信号时，该存储器在OSC0周期的1 / p倍的时间内将SRACT控制在H电平以激活RASB信号。 版权所有（C）2008，JPO＆INPIT