公开(公告)号：DE102004036455B4

公开(公告)日：2010-01-21

申请号：DE102004036455

申请日：2004-07-28

Applicant: ELPIDA MEMORY INC

Inventor： TAKAI YASUHIRO ,  KOBAYASHI SHOTARO

IPC: G06F1/10 ,  G11C11/407 ,  G11C11/4076 ,  H03K5/04 ,  H03K5/13 ,  H03L7/081 ,  H03L7/087

Abstract: A delay circuit includes a first delay line circuit having a plurality of stages of delay units, a second delay line circuit having a plurality of stages of delay units, a plurality of transfer circuits provided in association with respective stages of the delay units of the first delay line circuit, the transfer circuits controlling the transfer of the outputs of the delay units of the first delay line circuit to associated stages of the delay units of the second delay line circuit. The delay units of respective stages of the first delay line circuit inverting input signals. Each stage delay unit of the second delay line circuit includes a logic circuit receiving an output signal of the transfer circuit associated with the delay unit in question and an output signal of a preceding stage to send an output signal to a following stage. The duty ratio is rendered variable by independently selecting the rising edge of the input signal and a propagation path of the falling edge.

公开(公告)号：DE102004048690A1

公开(公告)日：2005-08-04

申请号：DE102004048690

申请日：2004-10-06

Applicant: ELPIDA MEMORY INC

Inventor： TAKAI YASUHIRO

IPC: G11C29/00 ,  G11C17/16 ,  G11C17/18 ,  H01L21/82 ,  G11C17/08

公开(公告)号：DE102004036455A1

公开(公告)日：2005-05-12

申请号：DE102004036455

申请日：2004-07-28

Applicant: ELPIDA MEMORY INC

Inventor： TAKAI YASUHIRO ,  KOBAYASHI SHOTARO

IPC: G06F1/10 ,  G11C11/407 ,  G11C11/4076 ,  H03K5/04 ,  H03K5/13 ,  H03L7/081 ,  H03L7/087 ,  H03K5/14

Abstract: A delay circuit includes a first delay line circuit having a plurality of stages of delay units, a second delay line circuit having a plurality of stages of delay units, a plurality of transfer circuits provided in association with respective stages of the delay units of the first delay line circuit, the transfer circuits controlling the transfer of the outputs of the delay units of the first delay line circuit to associated stages of the delay units of the second delay line circuit. The delay units of respective stages of the first delay line circuit inverting input signals. Each stage delay unit of the second delay line circuit includes a logic circuit receiving an output signal of the transfer circuit associated with the delay unit in question and an output signal of a preceding stage to send an output signal to a following stage. The duty ratio is rendered variable by independently selecting the rising edge of the input signal and a propagation path of the falling edge.

公开(公告)号：DE10244123A1

公开(公告)日：2003-04-24

申请号：DE10244123

申请日：2002-09-18

Applicant: ELPIDA MEMORY INC

Inventor： TAKAI YASUHIRO

IPC: G11C11/407 ,  G06F1/10 ,  G11C7/22 ,  G11C11/4076 ,  H03K5/00 ,  H03K5/13 ,  H03L7/08 ,  H03L7/081

Abstract: A multiplexer (35A) outputs signal with rising edge and falling edges based on the output of delay circuits (21,22,31,32). A delay lock loop (DLL) circuit (3) has phase detector (33) detecting phase difference of outputs of input buffer and buffer (38). A counter (34) outputs a signal to change output tap of the circuits (31,32) based on detector output. An Independent claim is also included for delay lock loop apparatus.

公开(公告)号：DE102008009622A1

公开(公告)日：2008-10-23

申请号：DE102008009622

申请日：2008-02-18

Applicant: ELPIDA MEMORY INC

Inventor： TAKAI YASUHIRO

IPC: H03K3/023 ,  H03B5/12 ,  H03K3/0231 ,  H03K5/08 ,  H03K5/26

Abstract: A voltage controlled oscillator that is a differential ring oscillator type voltage controlled oscillator that, by connecting in cascade differential delay elements to which differential clock signals of a mutually reverse phase are input and controlling the current that flows to the differential delay elements by a bias voltage, controls a delay amount of this differential clock signal, having a phase detection portion that outputs a detection signal by comparing an output voltage of the differential output of any differential delay element and a reference voltage that is set to a voltage that detects an abnormal operation, and a cross-coupled circuit that is provided at each of the differential delay elements and, when the detection signal is input, amplifies the potential difference between the pair of differential output terminals.

公开(公告)号：DE10242886A1

公开(公告)日：2003-06-05

申请号：DE10242886

申请日：2002-09-16

Applicant: ELPIDA MEMORY INC

Inventor： TAKAI YASUHIRO

IPC: G11C11/407 ,  G06F1/10 ,  G06F1/12 ,  G11C8/00 ,  G11C11/4076 ,  H03K5/13 ,  H03K5/131 ,  H03K5/15 ,  H03L7/081 ,  H03L7/089 ,  H04L7/033

Abstract: Disclosed is an interpolating circuit for producing an output signal having a delay time corresponding to a value obtained by performing interior division of a phase difference between entered first and second signals by a preset interior division ratio. The interpolating circuit includes a waveform synthesis unit and a bias control unit. The waveform synthesis unit includes an OR gate, which receives the first and second signals, for outputting the logic OR between these two signals; a first switch element inserted between a node, which is connected to an output terminal, and a first power supply and turned on and off by the output signal of the OR gate; a series circuit comprising a first constant-current source and a second switch element turned on and off by the first signal; and a series circuit comprising a second constant-current source and a third switch element turned on and off by the second signal; the series circuits being connected in parallel between the output node and a second power supply. On the basis of control signals that decide the interior division ratio, the bias control unit performs control in such a manner that current-path switches are turned on and off so that first and second current values, which are the totals of current values, will flow into the first and second constant-current sources, respectively.

公开(公告)号：DE10242886B4

公开(公告)日：2006-09-28

申请号：DE10242886

申请日：2002-09-16

Applicant: ELPIDA MEMORY INC

Inventor： TAKAI YASUHIRO

IPC: G11C11/407 ,  H04L7/033 ,  G06F1/10 ,  G06F1/12 ,  G11C8/00 ,  G11C11/4076 ,  H03K5/13 ,  H03K5/131 ,  H03K5/15 ,  H03L7/081 ,  H03L7/089

Abstract: Disclosed is an interpolating circuit for producing an output signal having a delay time corresponding to a value obtained by performing interior division of a phase difference between entered first and second signals by a preset interior division ratio. The interpolating circuit includes a waveform synthesis unit and a bias control unit. The waveform synthesis unit includes an OR gate, which receives the first and second signals, for outputting the logic OR between these two signals; a first switch element inserted between a node, which is connected to an output terminal, and a first power supply and turned on and off by the output signal of the OR gate; a series circuit comprising a first constant-current source and a second switch element turned on and off by the first signal; and a series circuit comprising a second constant-current source and a third switch element turned on and off by the second signal; the series circuits being connected in parallel between the output node and a second power supply. On the basis of control signals that decide the interior division ratio, the bias control unit performs control in such a manner that current-path switches are turned on and off so that first and second current values, which are the totals of current values, will flow into the first and second constant-current sources, respectively.

公开(公告)号：JP2009284266A

公开(公告)日：2009-12-03

申请号：JP2008134775

申请日：2008-05-22

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： TAKAI YASUHIRO

IPC: H03L7/081 ,  H03K5/135

CPC classification number: H03L7/0814 ,  H03K5/13 ,  H03K5/133 ,  H03K2005/00052 ,  H03L7/0818

Abstract: PROBLEM TO BE SOLVED: To provide a DLL circuit for reducing the minimum operation cycle of an interpolation circuit, and raising the maximum operating frequency of DLL.
SOLUTION: A phase detection circuit 21 detects the difference of phase between a reference clock signal to be input and a clock signal to be output from a replica circuit 17 to be output to a delay control circuit 22. The delay control circuit 22 outputs a control signal for adjusting the phase of the reference clock signal on the basis of a signal with phase difference. Then, multiplexers 12, 13 select and output a signal with delay difference for two stages of inverters from a coarse adjustment delay circuit 10 on the basis of the control signal to be output from the delay control circuit 22, and a first fine adjustment delay circuit 14 outputs a signal with delay difference for one stage of inverter on the basis of the signal with delay difference for two stages input from a multiplexer. A second fine adjustment delay circuit 15 adjusts the phase of the clock signal on the basis of the signal with delay difference for one stage.
COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供用于减小内插电路的最小操作周期并提高DLL的最大工作频率的DLL电路。 解决方案：相位检测电路21检测待输入的参考时钟信号与要从复制电路17输出的时钟信号之间的相位差，以输出到延迟控制电路22.延迟控制电路22 基于具有相位差的信号输出用于调整参考时钟信号的相位的控制信号。 然后，多路复用器12,13基于从延迟控制电路22输出的控制信号，从粗调延迟电路10选择并输出两级反相器的具有延迟差的信号，以及第一微调延迟电路 基于从多路复用器输入的两级具有延迟差的信号，输出一级逆变器的延迟差的信号。 第二微调延迟电路15基于具有一级延迟差的信号来调整时钟信号的相位。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2009152658A

公开(公告)日：2009-07-09

申请号：JP2007326220

申请日：2007-12-18

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： IDE AKIRA ,  TAKAI YASUHIRO ,  SEKIGUCHI TOMONORI ,  TAKEMURA RIICHIRO ,  AKIYAMA SATORU ,  NAKATANI HIROAKI

IPC: H03K19/0175 ,  G06F1/04 ,  G11C11/4076 ,  H01L21/8242 ,  H01L27/108 ,  H03K5/00 ,  H03K5/13 ,  H03K5/131

CPC classification number: G11C7/22 ,  G11C7/04 ,  G11C7/1048 ,  G11C7/12 ,  G11C7/20 ,  G11C7/222 ,  G11C11/4094 ,  H01L27/0207 ,  H01L27/108 ,  H01L27/10897 ,  H03K5/15066

Abstract: PROBLEM TO BE SOLVED: To provide a timing control circuit exhibiting a small timing variation for variation of power supply voltage or temperature, and to provide a semiconductor device equipped with that circuit. SOLUTION: A semiconductor device includes a first clock generation circuit and a second clock generation circuit employing an input clock, and a timing generation circuit receiving a first clock signal, a second clock signal, an activation signal from a command decoder, and a select signal for selecting a delay time from a timing register and generating a timing corresponding to a time combining a time equal to m times first period and a time equal to n times second period defined by the select signal from activation of the activation signal, wherein m and n are predetermined and the timing register stores the values of m and n, and storing in the timing register is carried out in an initialization sequence at the time of a mode register set command. Under an operating state, a timing signal is output at a desired timing from the timing generation circuit based on the information stored in the timing register. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供一种具有小的定时变化以用于电源电压或温度变化的定时控制电路，并提供配备有该电路的半导体器件。 解决方案：半导体器件包括采用输入时钟的第一时钟产生电路和第二时钟产生电路，以及从命令解码器接收第一时钟信号，第二时钟信号，激活信号的定时产生电路和 选择信号，用于从定时寄存器中选择延迟时间，并产生与组合等于第一周期m倍的时间的时间相对应的时间和等于由激活信号激活的选择信号定义的第n个时间段的时间的定时， 其中m和n是预定的，并且定时寄存器存储m和n的值，并且在模式寄存器设置命令时以初始化顺序执行在定时寄存器中的存储。 在运行状态下，基于存储在定时寄存器中的信息，从定时发生电路以期望的定时输出定时信号。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2009021704A

公开(公告)日：2009-01-29

申请号：JP2007181358

申请日：2007-07-10

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： KUROKI KOJI ,  TAKAI YASUHIRO

IPC: H03L7/085 ,  H03K5/05 ,  H03L7/081

CPC classification number: G11C11/4076 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0814 ,  H03L7/087

Abstract: PROBLEM TO BE SOLVED: To provide a duty detection circuit applicable to a multi-phase DLL circuit in which discharge speed and charging speed can be kept constant and a large potential difference appears on the detection line, and to provide a DLL circuit employing it. SOLUTION: The duty detection circuit comprising discharge transistors TR1 and TR2, charging transistors TR3 and TR4, detection lines LDUTYHB and LDUTYLB, and a comparison circuit COMP for detecting the potential difference of the detection lines is further provided with gate control circuits G11-G14 for controlling the discharge transistors TR1, TR2 and the charging transistors TR3, TR4 in response to an internal clock signal in an even cycle. The detection line is charged/discharged in response to the internal clock signal in the even cycle, the duty detection circuit is applicable to a multi-phase DLL circuit and the potential difference appearing on the detection line can be ensured sufficiently. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供一种适用于其中放电速度和充电速度可以保持恒定并且在检测线上出现大的电位差的多相DLL电路的占空比检测电路，并且提供DLL电路 雇用它 解决方案：包括放电晶体管TR1和TR2，充电晶体管TR3和TR4，检测线LDUTYHB和LDUTYLB的占空比检测电路和用于检测检测线的电位差的比较电路COMP还具有栅极控制电路G11 -G14，用于响应于偶数周期中的内部时钟信号来控制放电晶体管TR1，TR2和充电晶体管TR3，TR4。 检测线在偶数周期内响应于内部时钟信号进行充电/放电，占空比检测电路可应用于多相DLL电路，并且可以充分确保出现在检测线上的电位差。 版权所有（C）2009，JPO＆INPIT