公开(公告)号：JP2003223785A

公开(公告)日：2003-08-08

申请号：JP2002375804

申请日：2002-12-26

Applicant: ELPIDA MEMORY INC ,  ATI TECHNOLOGIES INC

Inventor： NAGASHIMA YASUSHI ,  MACRI JOSEPH DOMINIC

IPC: G11C11/401 ,  G11C7/10 ,  G11C7/22 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/4097

Abstract: PROBLEM TO BE SOLVED: To provide a DRAM device which can operate at higher speed and also realize miniaturization. SOLUTION: Two types of command interval specifications are defined as first and second command interval specifications. The first command interval specification is defined as the relationship between a preceding command and a following command that are issued for the same bank, while the second command interval specification is defined as the relationship between a preceding command and a following command that are issued for different banks, respectively. As for the second command interval specification, since target banks are different between a preceding command and a following command, the following command is executed during the column circuits precharge after the preceding command. Therefore, in the case of the second command interval specification, a command interval is substantially shortened. In addition, pairs of banks are defined as bank pairs, and are applied the first and the second command interval specifications, so that the DRAM device is small-sized. COPYRIGHT: (C)2003,JPO

公开(公告)号：DE10227806A1

公开(公告)日：2003-07-17

申请号：DE10227806

申请日：2002-06-21

Applicant: ELPIDA MEMORY INC ,  ATI TECHNOLOGIES INC

Inventor： NAGASHIMA OSAMU ,  MACRI JOSEPH DOMINIC

IPC: G11C11/401 ,  G11C7/10 ,  G11C7/22 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/4097

Abstract: Two types of command interval specifications are defined as first and second command interval specifications. The first command interval specifications is defined as the relationship between a preceding command and a following command that are issued for the same bank, while the second command interval specifications is defined as the relationship between a preceding command and a following command that are issued for different banks, respectively. As for the second command interval specification, since target banks are different between a preceding command and a following command, the following command is executed during the column circuits precharge after the preceding command. Therefore, in the case of the second command interval specification, a command interval is substantially shortened. In addition, pairs of banks are defined as bank pairs, and are applied the first and second command interval specifications, so that the DRAM device is small-sized.

公开(公告)号：DE10227806B4

公开(公告)日：2018-06-14

申请号：DE10227806

申请日：2002-06-21

Applicant: ELPIDA MEMORY INC ,  ATI TECH INC

Inventor： NAGASHIMA OSAMU ,  MACRI JOSEPH DOMINIC

IPC: G11C7/22 ,  G11C11/401 ,  G11C7/10 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/4097

Abstract: Verfahren zum Steuern eines Speicherchips (300), der mehrere Bänke aufweist, umfassend:Erzeugen eines Datenschreibbefehls zum Schreiben von Daten auf eine Zielbank und eines Datenlesebefehls zum Lesen von Daten von einer Zielbank, wobei die Zielbänke durch einen Aktivierungsbefehl aktiviert wurden;Feststellen, ob eine Speicherbank, welche die Zielbank des Datenschreibbefehls ist, mit einer Speicherbank, welche die Zielbank des Datenlesebefehls ist, übereinstimmt; undAusgeben des Datenschreibbefehls und danach des Datenlesebefehls an den Speicherchip (300), wobei der Datenlesebefehl nach einem ersten Zeitintervall ausgegeben wird, wenn die Zielbänke des Datenschreibbefehls und des Datenlesebefehls übereinstimmen, und nach einem zweiten Zeitintervall, das sich vom ersten Zeitintervall unterscheidet, wenn die Zielbänke des Datenschreibbefehls und des Datenlesebefehls nicht übereinstimmen.