公开(公告)号：DE10227806A1

公开(公告)日：2003-07-17

申请号：DE10227806

申请日：2002-06-21

Applicant: ELPIDA MEMORY INC ,  ATI TECHNOLOGIES INC

Inventor： NAGASHIMA OSAMU ,  MACRI JOSEPH DOMINIC

IPC: G11C11/401 ,  G11C7/10 ,  G11C7/22 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/4097

Abstract: Two types of command interval specifications are defined as first and second command interval specifications. The first command interval specifications is defined as the relationship between a preceding command and a following command that are issued for the same bank, while the second command interval specifications is defined as the relationship between a preceding command and a following command that are issued for different banks, respectively. As for the second command interval specification, since target banks are different between a preceding command and a following command, the following command is executed during the column circuits precharge after the preceding command. Therefore, in the case of the second command interval specification, a command interval is substantially shortened. In addition, pairs of banks are defined as bank pairs, and are applied the first and second command interval specifications, so that the DRAM device is small-sized.

公开(公告)号：JP2004310700A

公开(公告)日：2004-11-04

申请号：JP2003129584

申请日：2003-04-01

Applicant: Ati Technologies Inc ,  Elpida Memory Inc ,  エイティアイ テクノロジーズ インコーポレイテッド ,  エルピーダメモリ株式会社

Inventor： JOSEPH MACRI ,  DRAPKIN OLGE ,  TEMKINE GRIGORI ,  NAGASHIMA OSAMU

IPC: G06F12/00 ,  G11C11/401

Abstract: PROBLEM TO BE SOLVED: To prevent reduction of efficiency of data transfer caused by a large number of transitions in a signal level. SOLUTION: A current word is compared with a preceding word of N bits, and the number of bit transitions each from a low level value to a high level value, or contrarily from the high level value to the low level value is discriminated. When the number of the transitions is more than N/2, current bits are inverted. So as not to make an extra bit accompany a data byte for display of presence/absence of the inversion, a data mask pin normally unused in writing operation is practically used in order to send the inverted bits. COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：JP2010118087A

公开(公告)日：2010-05-27

申请号：JP2010048024

申请日：2010-03-04

Applicant: Ati Technologies Inc ,  Elpida Memory Inc ,  エイティアイ テクノロジーズ インコーポレイテッド ,  エルピーダメモリ株式会社

Inventor： JOSEPH MACRI ,  DRAPKIN OLGE ,  TEMKINE GRIGORI ,  NAGASHIMA OSAMU

IPC: G06F12/00

Abstract: PROBLEM TO BE SOLVED: To prevent an efficiency of data transfer from deteriorating caused by large number of transitions in a signal level. SOLUTION: A current word is compared with a preceding word of N bits, to identify the number of the bit transitions from a low level value to a high level value, or reversely from the high level value to the low level value. The current bits are inverted when the number of the transitions is more than N/2. A data mask pin not used usually during writing operation for sending the inverted bits is utilized not to make an extra bit go with a data bite for displaying the presence of the inversion. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：为了防止由信号电平中的大量转换引起的数据传输效率降低。 解决方案：将当前字与N位的前一个字进行比较，以识别从低电平值到高电平值的位转换的数量，或者从高电平值反向到低电平值。 当转换次数大于N / 2时，当前位被反转。 通常在用于发送反相位的写入操作期间不使用的数据掩码引脚不被用于显示反转的存在的数据咬入额外的位。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：DE60321612D1

公开(公告)日：2008-07-31

申请号：DE60321612

申请日：2003-02-10

Applicant: ATI TECHNOLOGIES INC ,  ELPIDA MEMORY INC

Inventor： MACRI JOSEPH ,  DRAPKIN OLEG ,  TEMKINE GRIGORI ,  NAGASHIMA OSAMU

IPC: G11C7/10 ,  G11C11/4096

公开(公告)号：JP2004310969A

公开(公告)日：2004-11-04

申请号：JP2003129585

申请日：2003-04-01

Applicant: Ati Technologies Inc ,  Elpida Memory Inc ,  エイティアイ テクノロジーズ インコーポレイテッド ,  エルピーダメモリ株式会社

Inventor： JOSEPH MACRI ,  DRAPKIN OLGE ,  TEMKINE GRIGORI ,  NAGASHIMA OSAMU

IPC: G06F3/00 ,  G11C11/401 ,  G11C11/407 ,  H03K19/0175 ,  H04L25/02

Abstract: PROBLEM TO BE SOLVED: To prevent ringing and line reflections in a memory device. SOLUTION: N-MOS transistors each of which has an impedance of two to eight times of the characteristic impedance of the communication path in a memory device such as a DRAM or an SDRAM are provided in the memory device. These N-MOS transistors perform self-terminations by enabling or disabling the memory device so as to eliminate ringing and line reflections. COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：DE10227806B4

公开(公告)日：2018-06-14

申请号：DE10227806

申请日：2002-06-21

Applicant: ELPIDA MEMORY INC ,  ATI TECH INC

Inventor： NAGASHIMA OSAMU ,  MACRI JOSEPH DOMINIC

IPC: G11C7/22 ,  G11C11/401 ,  G11C7/10 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/4097

Abstract: Verfahren zum Steuern eines Speicherchips (300), der mehrere Bänke aufweist, umfassend:Erzeugen eines Datenschreibbefehls zum Schreiben von Daten auf eine Zielbank und eines Datenlesebefehls zum Lesen von Daten von einer Zielbank, wobei die Zielbänke durch einen Aktivierungsbefehl aktiviert wurden;Feststellen, ob eine Speicherbank, welche die Zielbank des Datenschreibbefehls ist, mit einer Speicherbank, welche die Zielbank des Datenlesebefehls ist, übereinstimmt; undAusgeben des Datenschreibbefehls und danach des Datenlesebefehls an den Speicherchip (300), wobei der Datenlesebefehl nach einem ersten Zeitintervall ausgegeben wird, wenn die Zielbänke des Datenschreibbefehls und des Datenlesebefehls übereinstimmen, und nach einem zweiten Zeitintervall, das sich vom ersten Zeitintervall unterscheidet, wenn die Zielbänke des Datenschreibbefehls und des Datenlesebefehls nicht übereinstimmen.