公开(公告)号：IN4831CH2013A

公开(公告)日：2015-08-07

申请号：IN4831CH2013

申请日：2013-10-28

Applicant: EMPIRE TECHNOLOGY DEV LLC

Inventor： SRIRAM VAJAPEYAM

IPC: G06F9/00

Abstract: Technologies are generally described for methods and systems effective to execute a program in a multi-core processor. In an example, methods to execute a program in a multi-core processor may include executing a first procedure on a first core of a multi-core processor. The methods may further include while executing the first procedure, sending a first and second instruction, from the first core to a second and third core, respectively. The instructions may command the cores to execute second and third procedures. The methods may further include executing the first procedure on the first core while executing the second procedure on the second core and executing the third procedure on the third core.

公开(公告)号：IN4449CH2013A

公开(公告)日：2015-04-03

申请号：IN4449CH2013

申请日：2013-09-30

Applicant: EMPIRE TECHNOLOGY DEV LLC

Inventor： SRIRAM VAJAPEYAM

IPC: G06F12/00

Abstract: Techniques described herein are generally related to data transfer in multi-core processor devices. A first core of the multi-core processor device may be configured to receive a request for a data block. The requested data block may be stored in a private cache of the first core. The data block in the private cache may be evaluated by a coherence module of the first core to determine when the stored data block is in a ready state. A program slice associated with the data block may be identified by the coherence module when the stored data block is determined to be in an unavailable state and the identified program slice may be executed by the first core effective to update the stored data block from the unavailable state to the ready state. The data block may be sent to an interconnect network in response to the received request when the stored data block is determined to be in the ready state.