公开(公告)号：US20200006543A1

公开(公告)日：2020-01-02

申请号：US16453118

申请日：2019-06-26

Applicant: EPISTAR CORPORATION

Inventor： Shang-Ju TU ,  Chia-Cheng LIU ,  Tsung-Cheng CHANG ,  Ya-Yu YANG ,  Yu-Jiun SHEN ,  Jen-Inn CHYI

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/417

Abstract: A high electron mobility transistor, includes a substrate; a channel layer formed on the substrate; a barrier layer formed on the channel layer; a source electrode and a drain electrode formed on the barrier layer; a depletion layer formed on the barrier layer and between the source electrode and the drain electrode, wherein a material of the depletion layer comprises boron nitride or zinc oxide; and a gate electrode formed on the depletion layer.

公开(公告)号：US20210359123A1

公开(公告)日：2021-11-18

申请号：US17387433

申请日：2021-07-28

Applicant: EPISTAR CORPORATION

Inventor： Ya-Yu YANG ,  Shang-Ju TU ,  Tsung-Cheng CHANG ,  Chia-Cheng LIU

IPC: H01L29/78 ,  H01L29/778

Abstract: A semiconductor power device includes a substrate; a buffer structure formed on the substrate; a barrier structure formed on the buffer structure; a channel layer formed on the barrier structure; and a barrier layer formed on the channel layer; wherein the barrier structure includes a first functional layer on the buffer structure, a second functional layer formed between the first functional layer and the buffer structure, a first back-barrier layer on the first functional layer, and an interlayer between the first back-barrier layer and the first functional layer; wherein a material of the first back-barrier layer includes Alx1Ga1-x1N, a material of the first functional layer includes Alx2Ga1-x2N, a material of the interlayer includes Alx3Ga1-x3N, a material of the second functional layer includes Alx4Ga1-x4N, wherein 0

公开(公告)号：US20190103482A1

公开(公告)日：2019-04-04

申请号：US15720564

申请日：2017-09-29

Applicant: EPISTAR CORPORATION

Inventor： Ya-Yu YANG ,  Shang-Ju TU ,  Tsung-Cheng CHANG ,  Chia-Cheng LIU

IPC: H01L29/78

Abstract: A semiconductor power device includes a substrate, a buffer structure formed on the substrate, a barrier structure formed on the buffer structure, a channel layer formed on the barrier structure, and a barrier layer formed on the channel layer. The barrier structure includes a first functional layer on the buffer structure, a first back-barrier layer on the first functional layer, and an interlayer between the first back-barrier layer and the first functional layer. A material of the first back-barrier layer comprises Alx1Ga1-x1N, a material of the first functional layer comprises Alx2Ga1-x2N, 0

公开(公告)号：US20180033880A1

公开(公告)日：2018-02-01

申请号：US15664879

申请日：2017-07-31

Applicant: EPISTAR CORPORATION

Inventor： Ming-Chin CHEN ,  Yi-Chih LIN ,  Shang-Ju TU

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/10 ,  H01L29/205

CPC classification number: H01L29/7787 ,  H01L21/02458 ,  H01L21/0254 ,  H01L29/0611 ,  H01L29/0847 ,  H01L29/0891 ,  H01L29/1054 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41766 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/868

Abstract: This application provides a high power semiconductor device, which is characterized by forming two diodes connected in parallel and a schottky contact on a channel layer to lower the turn-on voltage and turn-on resistance of the high power semiconductor device at the same time and to enhance the breakdown voltage.

公开(公告)号：US20170154987A1

公开(公告)日：2017-06-01

申请号：US14953240

申请日：2015-11-27

Applicant: HUGA OPTOTECH INC. ,  EPISTAR CORPORATION

Inventor： Shang-Ju TU

IPC: H01L29/778 ,  H01L29/06 ,  H01L29/20 ,  H01L29/66

CPC classification number: H01L29/7787 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7786

Abstract: Disclosure includes a normally-off field-effect semiconductor device and the fabrication method thereof. An antigrowth portion is formed on a template. A first semiconductor layer and a second semiconductor layer on the template form two heterojunctions for creating two-dimensional electron gas regions, while a heterojunction-free area defined by the antigrowth portion separate the heterojunctions. A dielectric layer is on the second semiconductor layer and above the antigrowth portion. Two channel electrodes formed on the second semiconductor layer are electrically coupled to the two-dimensional electron gas regions respectively. A gate electrode on the dielectric layer and above the antigrowth portion is used for control of conduction between the channel electrodes.