公开(公告)号：FR2719928A1

公开(公告)日：1995-11-17

申请号：FR9405728

申请日：1994-05-10

Applicant: ESSILOR INT

Inventor： LEROUX THIERRY ,  MASSART CHRISTIAN

IPC: G09G3/20 ,  G09G3/36 ,  G09G5/39 ,  G09G5/399 ,  H04N5/66 ,  G06T5/00 ,  H04N1/40 ,  G02C13/00 ,  G09F9/35

Abstract: The method involves digitising a video signal (16) into components corresp. to odd and even frames and composite frame and line synchronisation signals. A memory (17) contg. even and odd portions is written synchronously under the influence of a graphics controller (18) in which a video synchronisation module (30) ensures detection of the useful window. A microprocessor (15) addresses the memory in both write and read modes. Readout is synchronised by a read module (32) and the signal generated for the matrix display (14) is transformed by a grey scale module (33) and a serialising interface module (34).

公开(公告)号：FR2719928B1

公开(公告)日：1996-08-02

申请号：FR9405728

申请日：1994-05-10

Applicant: ESSILOR INT

Inventor： LEROUX THIERRY ,  MASSART CHRISTIAN

IPC: G09G3/20 ,  G09G3/36 ,  G09G5/39 ,  G09G5/399 ,  H04N5/66 ,  G06T5/00 ,  H04N1/40 ,  G02C13/00 ,  G09F9/35

Abstract: The method involves digitising a video signal (16) into components corresp. to odd and even frames and composite frame and line synchronisation signals. A memory (17) contg. even and odd portions is written synchronously under the influence of a graphics controller (18) in which a video synchronisation module (30) ensures detection of the useful window. A microprocessor (15) addresses the memory in both write and read modes. Readout is synchronised by a read module (32) and the signal generated for the matrix display (14) is transformed by a grey scale module (33) and a serialising interface module (34).