Semiconductor nanowire fabrication

    公开(公告)号:GB2535418A

    公开(公告)日:2016-08-17

    申请号:GB201610764

    申请日:2014-12-08

    Applicant: IBM

    Abstract: Methods are provided for fabricating semiconductor nanowires 12, 40, 41, 45, 57 on a substrate 1, 20, 50. A nanowire template 3, 6; 22, 24; 31, 32 is formed on the substrate. The nanowire template defines an elongate tunnel 8, 26, 33 which extends, laterally over the substrate, between an opening 7, 25 in the template and a seed surface 10, 27, 34. The seed surface 10, 27, 34 is exposed to the tunnel and of area up to about 2x 4 10 nm 2. The semiconductor nanowire is selectively grown, via said opening, in the template from the seed surface. The area of the seed surface 10, 27, 34 is preferably such that growth of the nanowire proceeds from a single nucleation point on the seed surface.

    Method for manufacturing a semiconductor structure, semiconductor structure, and electronic device

    公开(公告)号:GB2532786A

    公开(公告)日:2016-06-01

    申请号:GB201421182

    申请日:2014-11-28

    Applicant: IBM

    Abstract: A method for manufacturing a semiconductor structure 1 comprises: providing a substrate 2 including a first semiconductor material; forming a dielectric layer 3 on a surface of the substrate 2; forming an opening in the dielectric layer 3 having a bottom reaching the substrate 2; providing a second semiconductor material 7B in the opening and on the substrate 2, the second semiconductor material 7B being encapsulated by a further dielectric material 6 forming a filled cavity; melting the second semiconductor material 7B in the cavity; recrystallizing the second semiconductor material 7B in the cavity; laterally removing the second semiconductor material 7B at least partially for forming a lateral surface at the second semiconductor material 7B; and forming a third semiconductor material 11 on the lateral surface of the second semiconductor material 7B. Also disclosed is the semiconductor structure 1 produced by the above method. The invention seeks to form compound semiconductor layers on silicon substrates without lattice mismatch deformations.

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