公开(公告)号：JP2010080816A

公开(公告)日：2010-04-08

申请号：JP2008249652

申请日：2008-09-29

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： ISHIKAWA SHIGEO

IPC: H01L21/316 ,  B24B7/22 ,  H01L21/02 ,  H01L21/304 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76829 ,  H01L21/304 ,  H01L21/76832 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor element favorably reduced in thickness as the semiconductor element capable of preventing a warp of a substrate caused by the grinding of the substrate from its rear face side after forming a semiconductor element structure on a substrate surface, and capable of performing dicing processing and being packaged with high integration.
SOLUTION: The semiconductor element includes a semiconductor element structure formed on the surface of the substrate 1 and a compensation stress film 6 formed at the semiconductor element structure to compensate for stress inducing the warp of the substrate 1 caused by the grinding of the substrate 1 from its rear face side.
COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：为了提供一种半导体元件，作为能够防止在基板上形成半导体元件结构之后从基板的背面磨削基板引起的翘曲的半导体元件，有利地减小厚度 表面，并且能够进行切割处理并且以高集成度被包装。 解决方案：半导体元件包括形成在基板1的表面上的半导体元件结构和形成在半导体元件结构处的补偿应力膜6，以补偿引起基板1的磨损引起的基板1的翘曲的应力 基板1从其背面侧。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2013197133A

公开(公告)日：2013-09-30

申请号：JP2012059640

申请日：2012-03-16

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： SUGIOKA SHIGERU ,  ISHIKAWA SHIGEO ,  MATSUDA YO

IPC: H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device having a capacitor in which a lower electrode of a cylinder shape is supported, and a method for manufacturing the same.SOLUTION: A method for manufacturing a semiconductor device includes the steps of: forming a first insulating film; forming a second insulating film covering an upper surface of the first insulating film; removing a part of the second insulating film so that a part of the first insulating film is exposed and an end surface of the second insulating film slants upward to an upper surface of the second insulating film; forming a third insulating film covering a part of the first insulating film and the upper surface of the second insulating film; forming a through hole which communicates with the first insulating film, the second insulating film, and the third insulating film, in which an opening partly overlaps at least a part of the first insulating film, and through which the second insulating film is exposed to an inner wall; forming a lower electrode covering the inner wall of the through hole and electrically connected to a semiconductor substrate; removing the first insulating film and the third insulating film; forming a capacitance insulating film; and forming an upper electrode.

Abstract translation: 要解决的问题：提供一种具有其中支撑有圆筒形状的下电极的电容器的半导体器件及其制造方法。解决方案：一种半导体器件的制造方法，包括以下步骤：形成第一 绝缘膜; 形成覆盖所述第一绝缘膜的上表面的第二绝缘膜; 去除所述第二绝缘膜的一部分，使得所述第一绝缘膜的一部分露出，并且所述第二绝缘膜的端面向上倾斜到所述第二绝缘膜的上表面; 形成覆盖所述第一绝缘膜的一部分和所述第二绝缘膜的上表面的第三绝缘膜; 形成与第一绝缘膜，第二绝缘膜和第三绝缘膜连通的通孔，其中开口部分地与第一绝缘膜的至少一部分重叠，并且第二绝缘膜通过其暴露于 内墙; 形成覆盖所述通孔的内壁并电连接到半导体衬底的下电极; 去除所述第一绝缘膜和所述第三绝缘膜; 形成电容绝缘膜; 并形成上电极。

公开(公告)号：JP2010262989A

公开(公告)日：2010-11-18

申请号：JP2009110882

申请日：2009-04-30

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： ISHIKAWA SHIGEO

IPC: H01L21/8242 ,  H01L21/318 ,  H01L27/108

CPC classification number: H01L28/90 ,  H01L21/7682 ,  H01L21/76829 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10852

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device including an insulating film for supporting a capacitor electrode or an interlayer dielectric for preventing the penetration of a chemical agent, wherein the insulating films are formed by depositing silicon nitride having chemical resistance to hydrofluoric acid and capable of being formed at a low temperature of ≤650°C.
SOLUTION: The method of manufacturing the semiconductor device includes: a step of forming a first interlayer dielectric comprising silicon nitride for preventing the penetration of a chemical agent on a lower interlayer dielectric embedded so that an upper end of a contact plug is exposed; a step of forming a second interlayer dielectric on the first interlayer dielectric; a step of forming a support insulating film comprising silicon nitride for holding the standing of lower electrodes of capacitor elements on the second interlayer dielectric; and a step of removing the second interlayer dielectric by wet etching while part of the support insulating film is left, and forming the lower electrodes of the capacitor elements. At least one of the first interlayer dielectric and the support insulating film is formed by using a high density plasma CVD method.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 解决的问题：提供一种制造半导体器件的方法，该半导体器件包括用于支撑用于防止化学试剂渗透的电容器电极或层间电介质的绝缘膜，其中绝缘膜通过沉积氮化硅而形成， 对氢氟酸具有耐化学腐蚀性，能够在≤650℃的低温下形成。 解决方案：制造半导体器件的方法包括：形成包含氮化硅的第一层间电介质的步骤，用于防止化学试剂渗透到嵌入的下层间电介质上，使得接触插塞的上端暴露 ; 在所述第一层间电介质上形成第二层间电介质的步骤; 形成包括氮化硅的支撑绝缘膜的步骤，用于保持第二层间电介质上的电容器元件的下电极的立场; 以及通过湿法蚀刻除去第二层间电介质的步骤，同时留下支撑绝缘膜的一部分，并形成电容器元件的下电极。 通过使用高密度等离子体CVD法形成第一层间电介质和支撑绝缘膜中的至少一个。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2008034673A

公开(公告)日：2008-02-14

申请号：JP2006207432

申请日：2006-07-31

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： ISHIKAWA SHIGEO

IPC: H01L21/316 ,  C23C16/40 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76837 ,  C23C16/0209 ,  C23C16/402 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/31608

Abstract: PROBLEM TO BE SOLVED: To solve a problem that in the case of directly forming an HDP-CVD oxide film on a metal wire for a semiconductor element, the metal wire is oxidized, and when the oxidation of the metal wire is prevented by a Si 3 N 4 film, wiring resistance may be increased. SOLUTION: In an HDP-CVD oxide film forming sequence, Ar gas is led into a reaction room and then source power (RF power) is applied to excite plasma. Then, carrier gas (He) is led into the reaction room. After heating a substrate by plasma of the Ar gas and the He gas, the leading of the Ar gas is stopped, SiH 4 gas and O 2 gas are simultaneously led into the reaction room, and bisa power is applied while lamping it. Since oxygen atmosphere gas is not led into the reaction room before starting film formation, oxidation of a W wire can be suppressed. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 解决的问题为了解决在半导体元件的金属线上直接形成HDP-CVD氧化膜的情况下，金属线被氧化，并且当金属线的氧化被阻止时 通过Si 3 4 膜，可以增加布线电阻。 解决方案：在HDP-CVD氧化膜形成顺序中，将Ar气引入反应室，然后施加源功率（RF功率）以激发等离子体。 然后，将载气（He）引入反应室。 在通过Ar气体和He气体的等离子体加热衬底之后，停止Ar气的引导，同时将SiH气体和O 2气体导入 反应室和bisa电源同时进行加压。 由于在开始成膜之前氧气气体不被引入反应室，所以可以抑制W丝的氧化。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2008159988A

公开(公告)日：2008-07-10

申请号：JP2006349319

申请日：2006-12-26

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： NAKAMURA YOSHITAKA ,  ARAO TAKASHI ,  MIYAHARA JIRO ,  ISHIKAWA SHIGEO ,  URABE KOJI

IPC: H01L21/8242 ,  H01L21/306 ,  H01L21/316 ,  H01L27/108

CPC classification number: H01L27/10894 ,  H01L27/10852 ,  H01L28/91

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device having a capacitor comprising a cylinder interlayer insulating film made of a two-layer interlayer insulating film, a charge storage capacitance of which is increased in the lower of a cylinder hole by making a hole diameter at the lower of the cylinder hole larger than the hole diameter at the upper, and moreover, a leakage current of which is low.
SOLUTION: An etching rate used for wet-etching of a first cylinder interlayer insulating film 23a is two times or higher, and lower than six times the etching rate used for wet-etching of a second cylinder interlayer insulating film 23b; the hole diameter of a first cylinder hole 50a is formed larger than the hole diameter of a second cylinder hole 50b; and the closer it is to a boundary 23c between the first cylinder interlayer insulating film 23a and the second cylinder interlayer insulating film 23b, the larger the hole diameter of the second cylinder hole 50b is formed in the vicinity of the boundary 23c.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种具有电容器的半导体器件，该电容器包括由双层层间绝缘膜制成的气缸层间绝缘膜，其电荷储存电容在气缸孔的下部增加， 气缸孔下部的孔直径大于上部的孔直径，另外漏电流低。 解决方案：用于第一气缸层间绝缘膜23a的湿蚀刻的蚀刻速率是第二气缸层间绝缘膜23b的湿蚀刻用蚀刻速度的两倍以上，低于六倍。 第一气缸孔50a的孔径形成为大于第二气缸孔50b的孔径; 并且越靠近第一气缸层间绝缘膜23a和第二气缸层间绝缘膜23b之间的边界23c，在边界23c附近形成第二气缸孔50b的孔径越大。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007305890A

公开(公告)日：2007-11-22

申请号：JP2006134703

申请日：2006-05-15

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： MORIOKA HITOSHI ,  ISHIKAWA SHIGEO

IPC: H01L21/31 ,  C23C16/44 ,  H05H1/46

CPC classification number: C23C16/45563 ,  C23C16/507 ,  H01J37/3244 ,  H01J37/32467 ,  H01J37/32871

Abstract: PROBLEM TO BE SOLVED: To solve problems wherein, in relation to an HDP-CVD (High-Density-Plasma CVD) apparatus which is utilized in manufacturing processes of semiconductor devices because of it excellent embeddability of the deposited material, the semiconductor manufacturing yield is decreased due to particle increase, and the uptime ratio of the apparatus is also decreased due to nozzle exchange for a short period of time, in the HDP-CVD apparatus operated under a high RF power condition. SOLUTION: The semiconductor manufacturing apparatus is provided with a gas-introducing nozzle in which aluminum nitride ceramic not containing yttria (Y 2 O 3 ) serving as a sintering aid is used as its material member. Since yittrium (Y) is not deposited on the nozzle surface, preferentially fluorinated region is reduced. Adhesiveness to a precoat film is thereby enhanced, and particle generation is suppressed during the film formation. Furthermore, since the portion that is easily fluorinated is reduced, fluorination of the entire nozzle is suppressed, and the life of the material member is extended. A semiconductor manufacturing apparatus with a high uptime ratio and a high manufacturing yield is then obtained. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：为了解决由于沉积材料具有优异的嵌入性而在半导体器件的制造工艺中使用的HDP-CVD（高密度 - 等离子体CVD）设备的问题，所以半导体 在高RF功率条件下操作的HDP-CVD装置中，由于颗粒增加，制造产量降低，并且由于喷嘴更换时间短，装置的正常运行时间比也降低。 解决方案：半导体制造装置设置有气体导入喷嘴，其中不含作为烧结助剂的氧化钇（Y 2 O 3 ）的氮化铝陶瓷 被用作其材料成员。 由于yittrium（Y）不沉积在喷嘴表面上，所以优先氟化区域减少。 从而提高了与预涂膜的粘合性，并且在成膜期间抑制了颗粒的产生。 此外，由于容易氟化的部分减少，所以喷嘴整体的氟化被抑制，并且材料部件的寿命延长。 然后获得具有高正常时间比和高制造成品率的半导体制造装置。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007059496A

公开(公告)日：2007-03-08

申请号：JP2005240576

申请日：2005-08-23

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： ASAOKA MINORU ,  HIROTA TOSHIYUKI ,  ISHIKAWA SHIGEO

IPC: H01L21/3065

Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device, capable of restraining any particle from being produced from a wafer edge by patterning a ground layer, using an amorphous carbon layer as a hard mask. SOLUTION: The manufacturing method comprises a process of sequentially forming the ground layer 12, an amorphous carbon layer 13a, and an intermediate mask layer 14a on a wafer 11; a process of forming a photoresist mask on the intermediate mask layer 14a; a process of forming the intermediate mask layer into an intermediate mask by patterning the intermediate mask layer 14a, using the photoresist mask as a mask; a process of forming the amorphous carbon layer 13a into a hard mask by patterning the amorphous carbon layer 13a, using the intermediate mask as a mask; and a process of patterning the ground layer 12 using the hard mask as a mask. In the process of forming the intermediate mask layer 14a, the edge of the intermediate mask layer 14a is deposited so as to protrude farther than the edge of the amorphous carbon layer 13a. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种半导体器件的制造方法，其能够通过使用无定形碳层作为硬掩模来图形化地层来抑制从晶片边缘产生的任何颗粒。 解决方案：制造方法包括在晶片11上依次形成接地层12，无定形碳层13a和中间掩模层14a的工艺; 在中间掩模层14a上形成光致抗蚀剂掩模的工艺; 通过使用光致抗蚀剂掩模作为掩模对中间掩模层14a进行图案化来将中间掩模层形成中间掩模的工艺; 使用中间掩模作为掩模，通过图案化无定形碳层13a来形成非晶碳层13a成为硬掩模的工艺; 以及使用硬掩模作为掩模对接地层12进行图案化的工序。 在形成中间掩模层14a的过程中，中间掩模层14a的边缘被沉积成比无定形碳层13a的边缘更远地突出。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2006310481A

公开(公告)日：2006-11-09

申请号：JP2005130089

申请日：2005-04-27

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： ISHIKAWA SHIGEO

IPC: H01L21/31 ,  C23C16/455

Abstract: PROBLEM TO BE SOLVED: To provide a plasma CVD apparatus capable of forming a thin film having a uniform film thickness distribution.
SOLUTION: The plasma CVD apparatus 10 introduces gas into a chamber 11 from 30 sets of nozzle devices 18 extending from a sidewall of the chamber, and a nozzle device 20 arranged in an upper part of a wafer stage 13. The nozzle device 20 in an upper part of the wafer stage 13 has four nozzle holes 25 which are arranged outside in the direction of 74° with respect to the vertical line, and in which a blow-off angle is directed in the direction of 60° with respect to the vertical line.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 解决的问题：提供能够形成具有均匀膜厚分布的薄膜的等离子体CVD装置。 解决方案：等离子体CVD装置10将气体从从腔室的侧壁延伸的30组喷嘴装置18和布置在晶片台13的上部的喷嘴装置20引入腔室11中。喷嘴装置 20在晶片台13的上部具有四个喷嘴孔25，它们相对于垂直线在74°的方向的外侧布置，并且其中吹扫角度相对于60°的方向指向 到垂直线。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2006120703A

公开(公告)日：2006-05-11

申请号：JP2004304439

申请日：2004-10-19

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： ISHIKAWA SHIGEO

IPC: H01L21/3205

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device which suppresses the warpage of a semiconductor board while preventing damage to the semiconductor element formation surface of the board in a semiconductor element forming process to eliminate troubles in a semiconductor element manufacturing process.
SOLUTION: The method for manufacturing the semiconductor device includes (a) a step of forming a protective layer 3 so that it covers a surface of the semiconductor board 1 having a warpage caused by a semiconductor element formed on the surface, (b) a step of forming a stress easing film 5 having a stress to reduce the warpage of the semiconductor board 1 so that the film 5 covers the backside of the semiconductor board 1, and (c) a step of eliminating the protective layer 3.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 解决的问题：提供一种制造半导体器件的方法，该半导体器件抑制半导体板的翘曲，同时防止在半导体元件形成工艺中损坏板的半导体元件形成表面以消除半导体元件中的故障 制造工艺。 解决方案：半导体器件的制造方法包括：（a）形成保护层3的工序，使其覆盖由形成在表面上的半导体元件引起的翘曲的半导体基板1的表面，（b ）形成具有应力的应力缓和膜5的步骤，以减少半导体板1的翘曲，使得膜5覆盖半导体板1的背面，以及（c）消除保护层3的步骤。 P>版权所有（C）2006，JPO＆NCIPI