公开(公告)号：US20240363693A1

公开(公告)日：2024-10-31

申请号：US18292860

申请日：2022-07-12

Applicant: Epinovatech AB

Inventor： Martin Andreas OLSSON

IPC: H01L29/201 ,  H01L21/02 ,  H01L27/092 ,  H01L29/20 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78

CPC classification number: H01L29/201 ,  H01L21/0254 ,  H01L29/2003 ,  H01L27/0928 ,  H01L29/66477 ,  H01L29/775 ,  H01L29/78

Abstract: A transistor (1) comprising a source (10), a body (12) and a drain (14), the transistor (1) further comprising a plurality of semiconductor layers (20), wherein layers of the plurality of semiconductor layers (20) are made of AlGaN or GaN, and wherein the plurality of semiconductor layers (20) is configured such that an aluminum content changes between each consecutive layer such that every second layer has a lower aluminum content than the neighboring mutually opposite layers thereof, wherein the transistor (1) is either a N-channel metal-oxide-semiconductor, NMOS, transistor (1′), wherein part of the plurality of semiconductor layers (20) is p-doped and forms part of the body (12) of the NMOS transistor (1′); or a P-channel metal-oxide-semiconductor, PMOS, transistor (1″), wherein part of the plurality of semiconductor layers (20) is p-doped and forms part of the source (10) or the drain (14) of the PMOS transistor (1″).

公开(公告)号：US20240186365A1

公开(公告)日：2024-06-06

申请号：US18556537

申请日：2022-04-20

Applicant: Epinovatech AB

Inventor： Martin Andreas OLSSON

IPC: H01L27/15 ,  H01L33/00 ,  H01L33/06 ,  H01L33/32

CPC classification number: H01L27/156 ,  H01L33/007 ,  H01L33/0093 ,  H01L33/06 ,  H01L33/32

Abstract: A method for forming a matrix of light-emitting diode (LED) elements (11, 21, 31) of different colours is provided. The method comprises epitaxially growing, on a GaN sacrificial layer (140), a first n-doped GaN layer (111), a first InxGa(1-X)N layer (112) and a first p-doped GaN layer (113) to form a first array of first LED elements (11) for emitting light of a first colour, and forming a first etch mask (151) comprising a plurality of first trenches (161). The method further comprises: epitaxially growing a second array of second LED elements (21), for emitting light of a second colour, in the plurality of first trenches; forming a second etch mask (152) protecting the second array and comprising a plurality of second trenches (162); and epitaxially growing a third array of third LED elements (31), for emitting light of a third colour, in the plurality of second trenches.

公开(公告)号：US20250169121A1

公开(公告)日：2025-05-22

申请号：US18841302

申请日：2023-02-23

Applicant: Epinovatech AB

Inventor： Martin Andreas OLSSON

IPC: H10D48/00 ,  G06N10/40 ,  H10D30/01 ,  H10D30/40 ,  H10D62/81 ,  H10D62/824

Abstract: The present inventive concept relates to a spin qubit transistor (100) comprising a base layer (102), a first qubit comprising, a first computing semiconductor island (106) and a first readout semiconductor island (108) arranged with a distance in the range of 3-10 nm therebetween, a second qubit comprising, a second computing semiconductor island (110) and a second readout semiconductor island (112) arranged with a distance in the range of 3-10 nm therebetween, wherein each of said semiconductor islands has a size causing each of said semiconductor islands to exhibit 3-dimensional quantum confinement of a single electron hole, and wherein each of said semiconductor islands forms a semiconductor heterojunction with the base layer. Each of the semiconductor islands has a corresponding gate (G1-G4), for modulation of the computing islands or readout of the readout islands. Said first computing semiconductor island and said second computing semiconductor island are configured to have a unique resonance frequency respectively. A control electrode arrangement (B) between the computing and the readout islands controls the coupling between the qubits. The present inventive concept further comprises a method for forming a spin qubit transistor and a quantum computer comprising at least one spin qubit transistor.

公开(公告)号：US20250040175A1

公开(公告)日：2025-01-30

申请号：US18713120

申请日：2022-11-23

Applicant: Epinovatech AB

Inventor： Martin Andreas OLSSON

IPC: H01L29/778 ,  H01L21/02 ,  H01L27/095 ,  H01L29/15 ,  H01L29/20 ,  H01L29/66

Abstract: A vertical high-electron-mobility transistor, HEMT (100), comprising: a substrate (310); a drain contact (410), the drain contact being a metal contact via through said substrate; a pillar layer (500) arranged above the drain contact (410) and comprising at least one vertical pillar (510) and a supporting material (520) laterally enclosing the at least one vertical pillar (510); a heterostructure mesa (600) arranged on the pillar layer (500), the heterostructure mesa (600) comprising an AlGaN-layer (610) and a GaN-layer (620), together forming a heterojunction (630); at least one source contact (420a, 420b) electrically connected to the heterostructure mesa (600); a gate contact (430) arranged on said heterostructure mesa (600), and above the at least one vertical pillar (510); wherein the at least one vertical pillar (510) is forming an electron transport channel between the drain contact (410) and the heterojunction (630).

公开(公告)号：US20250160056A1

公开(公告)日：2025-05-15

申请号：US18838581

申请日：2023-02-15

Applicant: EPINOVATECH AB

Inventor： Martin Andreas OLSSON

IPC: H10H20/812 ,  H10H20/01 ,  H10H20/825

Abstract: A device (1) for emitting light, the device (1) comprising: a substrate (2); abase layer (4) arranged on the substrate (2); a diode layer structure (10) arranged on the base layer (4), the diode layer structure (10) comprising a quantum well layer structure (30) sandwiched between an n-doped semiconductor layer (12) and a p-doped semiconductor layer (14); the quantum well layer structure (30) comprising a first (41) and second (42) quantum well, a first (51) and a second (52) proximal barrier layer, and a first (61) and a second (62) distal barrier layer, wherein the first (41) and second (42) quantum wells and the first (51) and second (52) proximal barrier layers are sandwiched between the first (61) and second (62) distal barrier layers

公开(公告)号：US20250063732A1

公开(公告)日：2025-02-20

申请号：US18720608

申请日：2022-12-13

Applicant: EPINOVATECH AB

Inventor： Martin Andreas OLSSON

IPC: H10B43/27 ,  H01L21/28 ,  H01L29/20 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792 ,  H10B43/30

Abstract: A memory device (1) comprising a semiconductor pillar (40) and at least one memory cell (50) associated with the pillar (40), wherein each of the at least one memory cells (50) comprises a charge trap (60) and a transistor (2), wherein. for each of the at least one memory cells (50): the charge trap (60) of the memory cell (50) is configured to control a threshold voltage of the transistor (2) of the memory cell (50) by a stored charge; and the transistor (2) of the memory cell (50) comprises a source pillar segment (10), a drain pillar segment (14) and a body pillar segment (12), wherein at least one p-doped pillar segment (10, 12, 14) of the transistor (2) comprises a plurality of semiconductor layers (20), wherein layers of the plurality of semiconductor layers (20) are made of AIGaN or GaN, and wherein the plurality of semiconductor layers (20) is configured such that every second layer has a lower aluminum content than the neighboring mutually opposite layers thereof.

公开(公告)号：US20240235412A1

公开(公告)日：2024-07-11

申请号：US18560299

申请日：2022-05-05

Applicant: Epinovatech AB

Inventor： Martin Andreas OLSSON ,  Andreas NORELIUS

IPC: H02M7/00 ,  H02M1/00 ,  H02M7/219 ,  H05K1/14

CPC classification number: H02M7/003 ,  H02M1/0077 ,  H02M7/219 ,  H05K1/144 ,  H05K2201/09209

Abstract: The present invention relates to a power converter device (1) comprising; a first circuit board (100), the first circuit board comprising a first driver (102) and at least four GaN HEMT devices (101) arranged in pairs (103, 104), said pairs connected in parallel; a second circuit board (200), the second circuit board comprising a second driver (202), and at least four MOSFET devices (201) arranged in pairs (203, 204), said pairs connected in parallel; the power converter device comprises at least two electrical connections (20) between the two circuit boards; wherein the first circuit board extends in a first plane and the second circuit board extends in a second plane, and the first and second circuit boards are arranged one above the other such that the two planes extends in parallel and the electrical connections between the two circuit boards extends in a direction substantially perpendicular to said first and second planes; and wherein said at least four GaN HEMT devices (101) are electrically connected equidistant to said first driver (102). The invention further relates to a system (2, 3) comprising such power converter device, and the use thereof.