公开(公告)号：DE69528099T2

公开(公告)日：2003-06-05

申请号：DE69528099

申请日：1995-03-10

Applicant: FRANCE TELECOM

Inventor： PAOLI MARYSE ,  BROUQUET PIERRE ,  HAOND MICHEL

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/316 ,  H01L21/76 ,  H01L21/762 ,  H01L21/768

Abstract: A method of isolating active zones of a semiconductor substrate by lateral trenches involves (1) forming, in the substrate (1), trenches (7) which are disposed laterally w.r.t. substrate regions (6) intended to form the active zones; (b) depositing a conformal insulating oxide layer (8) in the trenches (7) and on the regions (6); (c) carrying out a densifying anneal; (d) selectively etching to leave projecting conformal oxide zones on either side of each region (6) or group of regions; (e) subjecting the conformal oxide layer to partial mechanical-chemical polishing to reduce the height of the projecting zones to below the chosen residual relief height; and (f) exposing the regions (6) by chemical etching with detection of the end of etching. Also claimed is a semiconductor device with at least one trench-isolated active zone-forming region.

公开(公告)号：DE69528099D1

公开(公告)日：2002-10-17

申请号：DE69528099

申请日：1995-03-10

Applicant: FRANCE TELECOM

Inventor： PAOLI MARYSE ,  BROUQUET PIERRE ,  HAOND MICHEL

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/316 ,  H01L21/76 ,  H01L21/762 ,  H01L21/768

Abstract: A method of isolating active zones of a semiconductor substrate by lateral trenches involves (1) forming, in the substrate (1), trenches (7) which are disposed laterally w.r.t. substrate regions (6) intended to form the active zones; (b) depositing a conformal insulating oxide layer (8) in the trenches (7) and on the regions (6); (c) carrying out a densifying anneal; (d) selectively etching to leave projecting conformal oxide zones on either side of each region (6) or group of regions; (e) subjecting the conformal oxide layer to partial mechanical-chemical polishing to reduce the height of the projecting zones to below the chosen residual relief height; and (f) exposing the regions (6) by chemical etching with detection of the end of etching. Also claimed is a semiconductor device with at least one trench-isolated active zone-forming region.

公开(公告)号：DE69020819D1

公开(公告)日：1995-08-17

申请号：DE69020819

申请日：1990-08-09

Applicant: FRANCE TELECOM

Inventor： HAOND MICHEL ,  GALVIER JEAN

IPC: H01L21/3213 ,  H01L21/336 ,  H01L21/84 ,  H01L29/772

公开(公告)号：DE69528098T2

公开(公告)日：2003-06-05

申请号：DE69528098

申请日：1995-03-10

Applicant: FRANCE TELECOM

Inventor： PAOLI MARYSE ,  BROUQUET PIERRE ,  HAOND MICHEL

IPC: H01L21/76 ,  H01L21/304 ,  H01L21/316 ,  H01L21/318 ,  H01L21/762

Abstract: The semiconductor comprises substrate (1) with a central region (6) which is intended later to become an active region. The substrate is covered by two layers (7) containing an insulating material. This consists of two layers (8, 9) of oxide materials. The insulating material forms a boss (16) which projects above the plane of the major surface of the device, projecting less than 1000 Angstroms.

公开(公告)号：DE69528098D1

公开(公告)日：2002-10-17

申请号：DE69528098

申请日：1995-03-10

Applicant: FRANCE TELECOM

Inventor： PAOLI MARYSE ,  BROUQUET PIERRE ,  HAOND MICHEL

IPC: H01L21/76 ,  H01L21/304 ,  H01L21/316 ,  H01L21/318 ,  H01L21/762

Abstract: The semiconductor comprises substrate (1) with a central region (6) which is intended later to become an active region. The substrate is covered by two layers (7) containing an insulating material. This consists of two layers (8, 9) of oxide materials. The insulating material forms a boss (16) which projects above the plane of the major surface of the device, projecting less than 1000 Angstroms.

公开(公告)号：DE69017798T2

公开(公告)日：1995-12-07

申请号：DE69017798

申请日：1990-06-18

Applicant: FRANCE TELECOM

Inventor： HAOND MICHEL

IPC: H01L21/336 ,  H01L21/86 ,  H01L29/786 ,  H01L29/84 ,  H01L27/088

Abstract: The present invention relates to a MOS transistor formed in an insulated portion of a thin layer of monocrystalline silicon on an insulator, comprising at least one lateral strip (13, 14) highly doped with the type of conductivity of the compartment (3) in which the channel region is formed, this strip extending along the edge of the compartment and the edge of the source region (5), and being placed in short-circuit with the source region by the conducting source layer (11).

公开(公告)号：DE69119871T2

公开(公告)日：1996-11-28

申请号：DE69119871

申请日：1991-11-14

Applicant: FRANCE TELECOM

Inventor： HAOND MICHEL

IPC: H01L21/302 ,  H01L21/033 ,  H01L21/28 ,  H01L21/3065 ,  H01L21/308

公开(公告)号：DE69119871D1

公开(公告)日：1996-07-04

申请号：DE69119871

申请日：1991-11-14

Applicant: FRANCE TELECOM

Inventor： HAOND MICHEL

IPC: H01L21/302 ,  H01L21/033 ,  H01L21/28 ,  H01L21/3065 ,  H01L21/308

公开(公告)号：DE69020819T2

公开(公告)日：1996-01-11

申请号：DE69020819

申请日：1990-08-09

Applicant: FRANCE TELECOM

Inventor： HAOND MICHEL ,  GALVIER JEAN

IPC: H01L21/3213 ,  H01L21/336 ,  H01L21/84 ,  H01L29/772

公开(公告)号：DE69017798D1

公开(公告)日：1995-04-20

申请号：DE69017798

申请日：1990-06-18

Applicant: FRANCE TELECOM

Inventor： HAOND MICHEL

IPC: H01L21/336 ,  H01L21/86 ,  H01L29/786 ,  H01L29/84 ,  H01L27/088

Abstract: The present invention relates to a MOS transistor formed in an insulated portion of a thin layer of monocrystalline silicon on an insulator, comprising at least one lateral strip (13, 14) highly doped with the type of conductivity of the compartment (3) in which the channel region is formed, this strip extending along the edge of the compartment and the edge of the source region (5), and being placed in short-circuit with the source region by the conducting source layer (11).