公开(公告)号：EP2462671A1

公开(公告)日：2012-06-13

申请号：EP09848008.0

申请日：2009-08-06

Applicant: Freescale Semiconductor, Inc. ,  STMicroelectronics Srl

Inventor： BODE, Hubert ,  GIACOMINI, Mauro

IPC: H02H7/20

CPC classification number: H01L27/0285 ,  H03K19/00315

Abstract: An electronic device comprises an application circuit; a first supply rail having a first electric potential; a second supply rail having a second electric potential different from the first electric potential; at least one terminal having a third electric potential, connected to the application circuit; and a protection circuit for protecting the application circuit from an injected current. The protection circuit comprises a first conductive line connected between the at least one terminal and the first supply rail, the first conductive line comprising a first switch having a first control input; and a first voltage amplifier circuit having a first input connected to the at least one terminal, a second input connected to the second supply rail and a first output connected to the first control input.

公开(公告)号：EP2462671B1

公开(公告)日：2014-05-07

申请号：EP09848008.0

申请日：2009-08-06

Applicant: Freescale Semiconductor, Inc. ,  STMicroelectronics Srl

Inventor： BODE, Hubert ,  GIACOMINI, Mauro

IPC: H02H7/20 ,  H01L27/02 ,  H03K19/003

CPC classification number: H01L27/0285 ,  H03K19/00315

公开(公告)号：WO2010095003A1

公开(公告)日：2010-08-26

申请号：PCT/IB2009/050720

申请日：2009-02-23

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  BODE, Hubert ,  LAUDENBACH, Andreas ,  ROTH, Andreas

Inventor： BODE, Hubert ,  LAUDENBACH, Andreas ,  ROTH, Andreas

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/58

CPC classification number: H01L23/585 ,  H01L22/14 ,  H01L22/34 ,  H01L27/0921 ,  H01L2924/0002 ,  H01L2924/00

Abstract: AC50017EC-PCT-20090210-Specification.DOC 10 February 2009 - 12 - Freescale Confidential Proprietary Title: Semiconductor device with appraisal circuitry ABSTRACT OF THE DISCLOSURE A semiconductor device (20) comprises a substrate (22) provided with a doping of a first type, on which an electronic circuit (60) is provided surrounded by a circuit portion (62) of the substrate provided with a doping of a second type; at least one pad (30) for connecting the electronic circuit to an external device outside the substrate, surrounded by a pad portion (32) provided with a doping of the second type; a sensing device (50) comprising a sensor portion (52) of the substrate provided with a doping of the first type, for sensing a parameter forming a measure for a local electrical potential of the substrate; and an evaluation unit (24) connected to the sensing device, for providing an evaluation signal based on a difference between the parameter and a reference value. Figure 3

Abstract translation: 具有评估电路的半导体器件本发明的半导体器件（20）包括：衬底（22），其具有掺杂第一类型的衬底， 电子电路（60）被设置在被提供有第二类型的掺杂的衬底的电路部分（62）周围; 至少一个用于将所述电子电路连接到所述衬底外部的外部设备的焊盘（30），所述焊盘被设置有所述第二类型的掺杂的焊盘部分（32）围绕; 感测装置（50），包括具有所述第一类型的掺杂的所述衬底的传感器部分（52），用于感测形成所述衬底的局部电势的度量的参数; 以及连接到感测装置的评估单元（24），用于基于参数和参考值之间的差来提供评估信号。 图3

公开(公告)号：WO2011015903A1

公开(公告)日：2011-02-10

申请号：PCT/IB2009/053447

申请日：2009-08-06

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  ST MICROELECTRONICS SRL ,  BODE, Hubert ,  GIACOMINI, Mauro

Inventor： BODE, Hubert ,  GIACOMINI, Mauro

IPC: H02H7/20

CPC classification number: H01L27/0285 ,  H03K19/00315

Abstract: An electronic device (40) comprises an application circuit (42); a first supply rail (44) having a first electric potential; a second supply rail (46) having a second electric potential different from the first electric potential; at least one terminal (48) having a third electric potential, connected to the application circuit; and a protection circuit (50) for protecting the application circuit from an injected current. The protection circuit comprises a first conductive line (52) connected between the at least one terminal and the first supply rail, the first conductive line comprising a first switch (54) having a first control input (56); and a first voltage amplifier circuit (58) having a first input (60) connected to the at least one terminal, a second input (62) connected to the second supply rail and a first output (64) connected to the first control input.

Abstract translation: 电子设备（40）包括应用电路（42）; 具有第一电位的第一供电轨（44）; 具有不同于第一电位的第二电位的第二供电轨（46）; 至少一个具有第三电位的端子（48），连接到所述应用电路; 以及用于保护施加电路免受注入电流的保护电路（50）。 保护电路包括连接在至少一个端子和第一电源轨之间的第一导线（52），第一导线包括具有第一控制输入端（56）的第一开关（54）; 以及具有连接到所述至少一个端子的第一输入端（60）的第一电压放大器电路（58），连接到所述第二电源轨的第二输入端（62）和连接到所述第一控制输入端的第一输出端（64）。

公开(公告)号：WO2013156821A1

公开(公告)日：2013-10-24

申请号：PCT/IB2012/051993

申请日：2012-04-20

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  BODE, Hubert ,  LESBATS, Mathieu

Inventor： BODE, Hubert ,  LESBATS, Mathieu

IPC: H03K3/0233 ,  H03K3/037

CPC classification number: H03L7/06 ,  H03K3/0231 ,  H03K4/50

Abstract: An oscillator circuit (1) for providing an output clock signal (CLK) is described. The oscillator circuit comprising a voltage reference (Vref), a first current source (11), a first capacitor (12), a first capacitor switch (13), a second current source (21), a second capacitor (22), a second capacitor switch (23), a first comparator (15), a second comparator (25) and a flip-flop (30). The first comparator (15) comprises a first chopper-stabilized comparator (150) switchable between a compare phase and a zeroing phase in dependence on the output clock signal and arranged to operate in the compare phase in a first half-phase of the output clock signal to provide a first comparator output (16) from comparing the first capacitor voltage to the reference voltage and arranged to operate in the zeroing phase in the second half-phase. The second comparator (25) comprises a second chopper-stabilized comparator switchable between a respective compare phase and a respective zeroing phase in dependence on the output clock signal and arranged to operate in its compare phase in the second half-phase to obtain a second comparator output (26) from comparing the second capacitor voltage to the reference voltage and arranged to operate in its zeroing phase in the first half-phase.

Abstract translation: 描述了用于提供输出时钟信号（CLK）的振荡器电路（1）。 所述振荡器电路包括电压基准（Vref），第一电流源（11），第一电容器（12），第一电容器开关（13），第二电流源（21），第二电容器（22）， 第二电容器开关（23），第一比较器（15），第二比较器（25）和触发器（30）。 第一比较器（15）包括第一斩波稳定比较器（150），其可以根据输出时钟信号在比较相位和归零相位之间切换，并被布置成在输出时钟的第一半相位中的比较相位 信号以提供第一比较器输出（16），以将第一电容器电压与参考电压进行比较，并且被布置成在第二半相中的归零阶段中操作。 第二比较器（25）包括第二斩波稳定比较器，其可以根据输出时钟信号在相应的比较相位和相应的归零相位之间切换，并被布置为在第二半相位中的比较相位中工作，以获得第二比较器 输出（26）将第二电容器电压与参考电压进行比较，并将其布置成在第一半相中的其调零阶段中工作。

公开(公告)号：WO2012143758A1

公开(公告)日：2012-10-26

申请号：PCT/IB2011/051717

申请日：2011-04-20

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  BODE, Hubert

Inventor： BODE, Hubert

IPC: H03L7/183 ,  H03L7/099

CPC classification number: H03L7/08 ,  H03L7/183 ,  H03L7/1974

Abstract: A clock signal generation system (10) comprises a clock signal generating circuit (12) arranged to provide a first clock signal having a selectable first clock rate; a divider circuit (14) connected to receive the first clock signal and arranged to generate, depending on a division factor, a second clock signal from the first clock signal, having a constant second clock rate and being synchronized with the first clock signal; and a controller module (16) connected to the divider circuit and arranged to change the division factor when a different first clock rate is selected, to keep the second clock rate constant and the second clock signal synchronized with the first clock signal.

Abstract translation: 时钟信号发生系统（10）包括时钟信号发生电路（12），其被布置成提供具有可选择的第一时钟速率的第一时钟信号; 分频器电路（14），被连接以接收所述第一时钟信号并被布置为根据分频因子从所述第一时钟信号产生具有恒定的第二时钟速率并与所述第一时钟信号同步的第二时钟信号; 以及控制器模块（16），其连接到所述分频器电路并且被布置为当选择不同的第一时钟速率时改变所述分频因子，以保持所述第二时钟速率恒定并且所述第二时钟信号与所述第一时钟信号同步。

公开(公告)号：WO2013124711A1

公开(公告)日：2013-08-29

申请号：PCT/IB2012/050856

申请日：2012-02-24

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  BODE, Hubert

Inventor： BODE, Hubert

IPC: H01L23/52

CPC classification number: G01R31/2896 ,  G01R31/2853 ,  G05F1/462 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/49113 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A semiconductor device for use in a package comprising an output pin (310) and a reference pin (320) is described. The semiconductor device comprises a plurality of output pads (1 1 1, 1 12) bondable to the output pin (310), a plurality of reference pads (121, 122) bondable to the reference pin (320), and an output driver circuitry (400). The output driver circuitry (400) has a control terminal (400C) for receiving a control signal and arranged to drive the plurality of output pads (111, 112) relative to the plurality of reference pads (121, 122) in dependence on the control signal. The output driver circuitry comprises a plurality of driver sections (401, 402) and a selection circuitry (600). Each driver section is arranged to drive an output pad (111; 112) relative to the single reference pad (121; 122) in dependence on a respective section control signal. The plurality of reference pads (121, 122) is connected in a one-to-one relationship to the plurality of driver sections (401, 402). The plurality of output pads (111, 112) is connected in a one-to-one relationship to the plurality of driver sections (401, 402). The selection circuitry is arranged to provide the respective section control signals to the plurality of driver sections (401, 402) in dependence on at least one selection signal and the control signal. A packaged semiconductor device, a method of testing and a method of conditioning are also described.

Abstract translation: 描述了一种用于包括输出引脚（310）和参考引脚（320）的封装的半导体器件。 所述半导体器件包括可耦合到所述输出引脚（310）的多个输出焊盘（111,112），可耦合到所述基准引脚（320）的多个参考焊盘（121,122），以及输出驱动器电路 （400）。 输出驱动器电路（400）具有用于接收控制信号的控制端（400C），并且被配置为相对于多个参考焊盘（121,122）驱动多个输出焊盘（111,112），这取决于控制 信号。 输出驱动器电路包括多个驱动器部分（401,402）和选择电路（600）。 每个驱动器部分被布置成根据相应的部分控制信号相对于单个参考焊盘（121; 122）驱动输出焊盘（111; 112）。 多个参考焊盘（121,122）以一对一关系连接到多个驱动器部分（401,402）。 多个输出焊盘（111,112）以一对一关系连接到多个驱动器部分（401,402）。 选择电路被布置成根据至少一个选择信号和控制信号，向多个驱动器部分（401,402）提供相应的部分控制信号。 还描述了封装的半导体器件，测试方法和调节方法。

公开(公告)号：WO2013017913A1

公开(公告)日：2013-02-07

申请号：PCT/IB2011/053419

申请日：2011-08-01

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  LESBATS, Mathieu ,  BODE, Hubert ,  PENA BELLO, Rafael

Inventor： LESBATS, Mathieu ,  BODE, Hubert ,  PENA BELLO, Rafael

IPC: H03K19/0175 ,  H04L12/28

CPC classification number: H04L25/02 ,  H03K19/00361 ,  H03K19/017509

Abstract: A signalling circuit (50) for a signal channel of a communication network comprises a communication network terminal (52) connectable to the signal channel and to a voltage supply (54); an input terminal (56) connectable to receive a transmit signal; a driver device (58) comprising a first driver terminal (60) connected to the communication network terminal, a second driver terminal (62) connected to ground, and a driver control terminal (70) connected to the input terminal; wherein the driver device is arranged to connect the communication network terminal to ground (64) in response to a transition from a low to a high voltage driver control signal state of a driver control signal received at the driver control terminal. And the signalling circuit comprises a feedback circuit (72) connected to the first driver terminal and the driver control terminal and comprising a capacitive device (74); and a pull-down device (76) arranged to connect the driver control terminal to ground (66) after a predefined delay after a transition of the transmit signal from a low to a high voltage transmit signal state.

Abstract translation: 用于通信网络的信号信道的信令电路（50）包括可连接到信号信道的通信网络终端（52）和电压源（54）; 可连接以接收发射信号的输入端（56） 驱动器装置（58），包括连接到通信网络终端的第一驱动器端子（60），连接到地的第二驱动器端子（62）和连接到输入端子的驱动器控制端子（70） 其中所述驱动器装置被布置成响应于从所述驾驶员控制终端处接收到的驾驶员控制信号的低电平到高电压驱动器控制信号状态的转变而将所述通信网络终端连接到地（64）。 并且信令电路包括连接到第一驱动器端子和驱动器控制端子并包括电容性装置（74）的反馈电路（72）。 以及下拉装置（76），其布置成在从低电压发送信号状态转换到高电压发送信号状态之后的预定义的延迟之后将驱动器控制端子接地（66）。

公开(公告)号：WO2015001388A1

公开(公告)日：2015-01-08

申请号：PCT/IB2013/055468

申请日：2013-07-04

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  BODE, Hubert ,  WENDEL, Dirk

Inventor： BODE, Hubert ,  WENDEL, Dirk

IPC: H03K3/02

CPC classification number: G06F1/08 ,  H03K3/023 ,  H03K3/0231

Abstract: An oscillator circuit (201) of the type comprising a flip-flop (219) for generating a clock signal (222) and two comparators (213, 216) for comparing a reference voltage with the voltage across a first capacitor which is charged during a first cycle of the clock signal and the voltage across a second capacitor which is charged during a second cycle of a clock signal provides a means for removing the effects of any offset in either comparator. This is achieved by reversing the inputs of the comparators (213, 216) for each cycle of the output frequency. Thus an offset in a comparator which would increase the clock period on one cycle will reduce the period of the next cycle by the same amount (due to the fact that any offset drift tends to evolve slowly compared with the output clock frequency). As a net result, the period of time over two clock periods will stay constant regardless of any offset drift in a comparator.

Abstract translation: 一种振荡器电路（201），包括用于产生时钟信号的触发器（219）和两个比较器（213,216），用于将参考电压与在第一电容器 时钟信号的第一周期和在时钟信号的第二周期期间被充电的第二电容器两端的电压提供了用于消除任一比较器中的任何偏移的影响的装置。 这通过对输出频率的每个周期的比较器（213,216）的输入进行反转来实现。 因此，将在一个周期上增加时钟周期的比较器中的偏移将使下一个周期的周期减少相同的量（由于任何偏移漂移趋向于与输出时钟频率相比慢地演变的事实）。 作为最终结果，无论比较器中有任何偏移漂移，两个时钟周期的时间段将保持不变。

公开(公告)号：WO2009072041A1

公开(公告)日：2009-06-11

申请号：PCT/IB2008/054987

申请日：2008-11-27

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  ROTH, Andreas ,  BODE, Hubert ,  LAUDENBACH, Andreas ,  LEHMANN, Stephan ,  WITTICH, Engelbert

Inventor： ROTH, Andreas ,  BODE, Hubert ,  LAUDENBACH, Andreas ,  LEHMANN, Stephan ,  WITTICH, Engelbert

IPC: H03K17/0814 ,  H03K19/003

CPC classification number: H03K19/00346 ,  G06F21/755

Abstract: A semiconductor device includes a substrate (1 ) on which an electronic circuit (40) is provided. Two or more pads may be present which can connect the electronic circuit to an external device outside the substrate. A current meter (50) is electrically in contact with at least a part of the substrate and/or the pad. The meter can measure a parameter forming a measure for an aggregate amount of a current flowing between the substrate and said pads. A control unit (60) is connected to the current meter (50) and the electronic circuit (40), for controlling the electronic circuit based on the measured parameter.

Abstract translation: 半导体器件包括其上设置有电子电路（40）的衬底（1）。 可以存在可以将电子电路连接到衬底外部的外部设备的两个或更多个焊盘。 电流表（50）与衬底和/或衬垫的至少一部分电接触。 仪表可以测量形成在基板和所述焊盘之间流动的电流的总量的度量的参数。 控制单元（60）连接到电流计（50）和电子电路（40），用于基于测量的参数来控制电子电路。